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frontend/ir_emitter: Add half-precision opcode for FPRecipEstimate

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Lioncash 2019-04-13 19:00:49 -04:00 committed by MerryMage
parent af2e5afed6
commit 2184d24e8f
5 changed files with 17 additions and 4 deletions
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4
src/backend/x64/emit_x64_floating_point.cpp
View file

@ -754,6 +754,10 @@ static void EmitFPRecipEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* i
code.CallFunction(&FP::FPRecipEstimate<FPT>);
}
void EmitX64::EmitFPRecipEstimate16(EmitContext& ctx, IR::Inst* inst) {
EmitFPRecipEstimate<u16>(code, ctx, inst);
}
void EmitX64::EmitFPRecipEstimate32(EmitContext& ctx, IR::Inst* inst) {
EmitFPRecipEstimate<u32>(code, ctx, inst);
}

13
src/frontend/ir/ir_emitter.cpp
View file

@ -1922,11 +1922,18 @@ U16U32U64 IREmitter::FPNeg(const U16U32U64& a) {
}
}
U32U64 IREmitter::FPRecipEstimate(const U32U64& a) {
if (a.GetType() == Type::U32) {
U16U32U64 IREmitter::FPRecipEstimate(const U16U32U64& a) {
switch (a.GetType()) {
case Type::U16:
return Inst<U16>(Opcode::FPRecipEstimate16, a);
case Type::U32:
return Inst<U32>(Opcode::FPRecipEstimate32, a);
case Type::U64:
return Inst<U64>(Opcode::FPRecipEstimate64, a);
default:
UNREACHABLE();
return U16U32U64{};
}
return Inst<U64>(Opcode::FPRecipEstimate64, a);
}
U16U32U64 IREmitter::FPRecipExponent(const U16U32U64& a) {

2
src/frontend/ir/ir_emitter.h
View file

@ -305,7 +305,7 @@ public:
U16U32U64 FPMulAdd(const U16U32U64& addend, const U16U32U64& op1, const U16U32U64& op2, bool fpcr_controlled);
U32U64 FPMulX(const U32U64& a, const U32U64& b);
U16U32U64 FPNeg(const U16U32U64& a);
U32U64 FPRecipEstimate(const U32U64& a);
U16U32U64 FPRecipEstimate(const U16U32U64& a);
U16U32U64 FPRecipExponent(const U16U32U64& a);
U16U32U64 FPRecipStepFused(const U16U32U64& a, const U16U32U64& b);
U16U32U64 FPRoundInt(const U16U32U64& a, FP::RoundingMode rounding, bool exact);

1
src/frontend/ir/microinstruction.cpp
View file

@ -272,6 +272,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
case Opcode::FPMulAdd16:
case Opcode::FPMulAdd32:
case Opcode::FPMulAdd64:
case Opcode::FPRecipEstimate16:
case Opcode::FPRecipEstimate32:
case Opcode::FPRecipEstimate64:
case Opcode::FPRecipExponent16:

1
src/frontend/ir/opcodes.inc
View file

@ -491,6 +491,7 @@ OPCODE(FPMulX64, U64, U64,
OPCODE(FPNeg16, U16, U16 )
OPCODE(FPNeg32, U32, U32 )
OPCODE(FPNeg64, U64, U64 )
OPCODE(FPRecipEstimate16, U16, U16 )
OPCODE(FPRecipEstimate32, U32, U32 )
OPCODE(FPRecipEstimate64, U64, U64 )
OPCODE(FPRecipExponent16, U16, U16 )