Implement thumb1_SBC_reg

This commit is contained in:
MerryMage 2016-07-09 08:27:41 +08:00
parent 1953e44532
commit 207cb74dc9
3 changed files with 19 additions and 2 deletions

View file

@ -56,7 +56,7 @@ private:
}; };
template <typename V> template <typename V>
static const std::array<Thumb1Matcher<V>, 19> g_thumb1_instruction_table {{ static const std::array<Thumb1Matcher<V>, 20> g_thumb1_instruction_table {{
#define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring) #define INST(fn, name, bitstring) detail::detail<Thumb1Matcher, u16, 16>::GetMatcher<decltype(fn), fn>(name, bitstring)
@ -80,7 +80,7 @@ static const std::array<Thumb1Matcher<V>, 19> g_thumb1_instruction_table {{
{ INST(&V::thumb1_LSR_reg, "LSR (reg)", "0100000011mmmddd") }, { INST(&V::thumb1_LSR_reg, "LSR (reg)", "0100000011mmmddd") },
{ INST(&V::thumb1_ASR_reg, "ASR (reg)", "0100000100mmmddd") }, { INST(&V::thumb1_ASR_reg, "ASR (reg)", "0100000100mmmddd") },
{ INST(&V::thumb1_ADC_reg, "ADC (reg)", "0100000101mmmddd") }, { INST(&V::thumb1_ADC_reg, "ADC (reg)", "0100000101mmmddd") },
//{ INST(&V::thumb1_SBCS_rr, "SBCS (rr)", "0100000110mmmddd") }, { INST(&V::thumb1_SBC_reg, "SBC (reg)", "0100000110mmmddd") },
//{ INST(&V::thumb1_RORS_rr, "RORS (rr)", "0100000111sssddd") }, //{ INST(&V::thumb1_RORS_rr, "RORS (rr)", "0100000111sssddd") },
//{ INST(&V::thumb1_TST_rr, "TST (rr)", "0100001000mmmnnn") }, //{ INST(&V::thumb1_TST_rr, "TST (rr)", "0100001000mmmnnn") },
//{ INST(&V::thumb1_NEGS_rr, "NEGS (rr)", "0100001001mmmddd") }, //{ INST(&V::thumb1_NEGS_rr, "NEGS (rr)", "0100001001mmmddd") },

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@ -170,6 +170,10 @@ public:
return Common::StringFromFormat("adcs %s, %s", RegStr(d_n), RegStr(m)); return Common::StringFromFormat("adcs %s, %s", RegStr(d_n), RegStr(m));
} }
std::string thumb1_SBC_reg(Reg m, Reg d_n) {
return Common::StringFromFormat("sbcs %s, %s", RegStr(d_n), RegStr(m));
}
std::string thumb1_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) { std::string thumb1_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo; Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;
return Common::StringFromFormat("add %s, %s", RegStr(d_n), RegStr(m)); return Common::StringFromFormat("add %s, %s", RegStr(d_n), RegStr(m));

View file

@ -226,6 +226,19 @@ struct TranslatorVisitor final {
ir.SetVFlag(result.overflow); ir.SetVFlag(result.overflow);
return true; return true;
} }
bool thumb1_SBC_reg(Reg m, Reg d_n) {
Reg d = d_n, n = d_n;
// SBCS <Rdn>, <Rm>
// Note that it is not possible to encode Rd == R15.
auto aspr_c = ir.GetCFlag();
auto result = ir.SubWithCarry(ir.GetRegister(n), ir.GetRegister(m), aspr_c);
ir.SetRegister(d, result.result);
ir.SetNFlag(ir.MostSignificantBit(result.result));
ir.SetZFlag(ir.IsZero(result.result));
ir.SetCFlag(result.carry);
ir.SetVFlag(result.overflow);
return true;
}
bool thumb1_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) { bool thumb1_ADD_reg_t2(bool d_n_hi, Reg m, Reg d_n_lo) {
Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo; Reg d_n = d_n_hi ? (d_n_lo + 8) : d_n_lo;