diff --git a/include/dynarmic/A64/a64.h b/include/dynarmic/A64/a64.h
index f51f6fad..5a84e4e0 100644
--- a/include/dynarmic/A64/a64.h
+++ b/include/dynarmic/A64/a64.h
@@ -105,6 +105,8 @@ public:
     /// Modify PSTATE
     void SetPstate(std::uint32_t value);
 
+    void ChangeProcessorID(std::size_t new_processor);
+
     /// Clears exclusive state for this core.
     void ClearExclusiveState();
 
diff --git a/src/backend/x64/a64_emit_x64.h b/src/backend/x64/a64_emit_x64.h
index c8fd2566..71dbbf2f 100644
--- a/src/backend/x64/a64_emit_x64.h
+++ b/src/backend/x64/a64_emit_x64.h
@@ -47,8 +47,12 @@ public:
 
     void InvalidateCacheRanges(const boost::icl::interval_set<u64>& ranges);
 
+    void ChangeProcessorID(size_t value) {
+        conf.processor_id = value;
+    }
+
 protected:
-    const A64::UserConfig conf;
+    A64::UserConfig conf;
     A64::Jit* jit_interface;
     BlockRangeInformation<u64> block_ranges;
 
diff --git a/src/backend/x64/a64_interface.cpp b/src/backend/x64/a64_interface.cpp
index ee1763a4..2986fcbe 100644
--- a/src/backend/x64/a64_interface.cpp
+++ b/src/backend/x64/a64_interface.cpp
@@ -185,6 +185,11 @@ public:
         jit_state.SetPstate(value);
     }
 
+    void ChangeProcessorID(size_t value) {
+        conf.processor_id = value;
+        emitter.ChangeProcessorID(value);
+    }
+
     void ClearExclusiveState() {
         jit_state.exclusive_state = 0;
     }
@@ -379,6 +384,10 @@ void Jit::SetPstate(u32 value) {
     impl->SetPstate(value);
 }
 
+void Jit::ChangeProcessorID(size_t new_processor) {
+    impl->ChangeProcessorID(new_processor);
+}
+
 void Jit::ClearExclusiveState() {
     impl->ClearExclusiveState();
 }