suyu/dynarmic
28
1
Fork 1
Code Issues Pull requests Projects Releases Packages Wiki Activity

A64: Implement SRSRA (scalar)

Browse source
This commit is contained in:
Lioncash 2018-05-11 10:31:30 -04:00 committed by MerryMage
parent 998aef07f6
commit 1e70a589b0
2 changed files with 29 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/frontend/A64/decoder/a64.inc
View file

@ -471,7 +471,7 @@ INST(CMEQ_reg_1, "CMEQ (register)", "01111
INST(SSHR_1, "SSHR", "010111110IIIIiii000001nnnnnddddd")
INST(SSRA_1, "SSRA", "010111110IIIIiii000101nnnnnddddd")
INST(SRSHR_1, "SRSHR", "010111110IIIIiii001001nnnnnddddd")
//INST(SRSRA_1, "SRSRA", "010111110IIIIiii001101nnnnnddddd")
INST(SRSRA_1, "SRSRA", "010111110IIIIiii001101nnnnnddddd")
INST(SHL_1, "SHL", "010111110IIIIiii010101nnnnnddddd")
//INST(SQSHL_imm_1, "SQSHL (immediate)", "010111110IIIIiii011101nnnnnddddd")
//INST(SQSHRN_1, "SQSHRN, SQSHRN2", "010111110IIIIiii100101nnnnnddddd")

34
src/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
View file

@ -39,6 +39,26 @@ static void ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, V
v.V_scalar(esize, Vd, result);
}
static void RoundingShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd,
ShiftExtraBehavior behavior) {
const size_t esize = 64;
const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend());
const IR::U64 operand = v.V_scalar(esize, Vn);
const IR::U64 round_bit = v.ir.LogicalShiftRight(v.ir.LogicalShiftLeft(operand, v.ir.Imm8(64 - shift_amount)), v.ir.Imm8(63));
const IR::U64 result = [&] {
IR::U64 tmp = v.ir.Add(v.ir.ArithmeticShiftRight(operand, v.ir.Imm8(shift_amount)), round_bit);
if (behavior == ShiftExtraBehavior::Accumulate) {
tmp = v.ir.Add(tmp, v.V_scalar(esize, Vd));
}
return tmp;
}();
v.V_scalar(esize, Vd, result);
}
enum class ShiftDirection {
Left,
Right,
@ -102,14 +122,16 @@ bool TranslatorVisitor::SRSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
return ReservedValue();
}
const size_t esize = 64;
const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend());
RoundingShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::None);
return true;
}
const IR::U64 operand = V_scalar(esize, Vn);
const IR::U64 round_bit = ir.LogicalShiftRight(ir.LogicalShiftLeft(operand, ir.Imm8(64 - shift_amount)), ir.Imm8(63));
const IR::U64 result = ir.Add(ir.ArithmeticShiftRight(operand, ir.Imm8(shift_amount)), round_bit);
bool TranslatorVisitor::SRSRA_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
if (!immh.Bit<3>()) {
return ReservedValue();
}
V_scalar(esize, Vd, result);
RoundingShiftRight(*this, immh, immb, Vn, Vd, ShiftExtraBehavior::Accumulate);
return true;
}