From 192a0fba7a3a5f57514567161e3ac6314c50c106 Mon Sep 17 00:00:00 2001 From: bunnei Date: Thu, 4 Aug 2016 23:12:11 -0400 Subject: [PATCH] arm: Implement LDRB reg/imm instructions. --- src/frontend/decoder/arm.h | 4 +-- .../translate/translate_arm/load_store.cpp | 29 +++++++++++++++++-- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/src/frontend/decoder/arm.h b/src/frontend/decoder/arm.h index 95802411..2b8972d2 100644 --- a/src/frontend/decoder/arm.h +++ b/src/frontend/decoder/arm.h @@ -179,8 +179,8 @@ boost::optional&> DecodeArm(u32 instruction) { // Load/Store instructions INST(&V::arm_LDR_imm, "LDR (imm)", "cccc010pu0w1nnnnddddvvvvvvvvvvvv"), INST(&V::arm_LDR_reg, "LDR (reg)", "cccc011pu0w1nnnnddddvvvvvrr0mmmm"), - //INST(&V::arm_LDRB_imm, "LDRB (imm)", "cccc010pu1w1nnnnddddvvvvvvvvvvvv"), - //INST(&V::arm_LDRB_reg, "LDRB (reg)", "cccc011pu1w1nnnnddddvvvvvrr0mmmm"), + INST(&V::arm_LDRB_imm, "LDRB (imm)", "cccc010pu1w1nnnnddddvvvvvvvvvvvv"), + INST(&V::arm_LDRB_reg, "LDRB (reg)", "cccc011pu1w1nnnnddddvvvvvrr0mmmm"), //INST(&V::arm_LDRBT, "LDRBT (A1)", "cccc0100u111nnnnttttvvvvvvvvvvvv"), //INST(&V::arm_LDRBT, "LDRBT (A2)", "cccc0110u111nnnnttttvvvvvrr0mmmm"), //INST(&V::arm_LDRD_imm, "LDRD (imm)", "cccc000pu1w0nnnnddddvvvv1101vvvv"), // v5E diff --git a/src/frontend/translate/translate_arm/load_store.cpp b/src/frontend/translate/translate_arm/load_store.cpp index 898d2f90..616e12c8 100644 --- a/src/frontend/translate/translate_arm/load_store.cpp +++ b/src/frontend/translate/translate_arm/load_store.cpp @@ -72,11 +72,36 @@ bool ArmTranslatorVisitor::arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n, } bool ArmTranslatorVisitor::arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm12 imm12) { - return InterpretThisInstruction(); + if (ConditionPassed(cond)) { + const auto data = ir.ReadMemory8(GetAddressingMode(ir, P, U, W, n, ir.Imm32(imm12))); + + if (d == Reg::PC) { + ir.ALUWritePC(ir.Add(data, ir.Imm32(4))); + ir.SetTerm(IR::Term::ReturnToDispatch{}); + return false; + } + + ir.SetRegister(d, data); + } + + return true; } bool ArmTranslatorVisitor::arm_LDRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg d, Imm5 imm5, ShiftType shift, Reg m) { - return InterpretThisInstruction(); + if (ConditionPassed(cond)) { + const auto shifted = EmitImmShift(ir.GetRegister(m), shift, imm5, ir.GetCFlag()); + const auto data = ir.ReadMemory8(GetAddressingMode(ir, P, U, W, n, shifted.result)); + + if (d == Reg::PC) { + ir.ALUWritePC(ir.Add(data, ir.Imm32(4))); + ir.SetTerm(IR::Term::ReturnToDispatch{}); + return false; + } + + ir.SetRegister(d, data); + } + + return true; } bool ArmTranslatorVisitor::arm_LDRBT() {