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A64: Implement SHA1M

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Lioncash 2018-04-15 21:38:55 -04:00 committed by MerryMage
parent 47bc97a71b
commit 181c3b0790
2 changed files with 12 additions and 1 deletions
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2
src/frontend/A64/decoder/a64.inc
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@ -324,7 +324,7 @@ INST(AESIMC, "AESIMC", "01001
// Data Processing - FP and SIMD - SHA
INST(SHA1C, "SHA1C", "01011110000mmmmm000000nnnnnddddd")
INST(SHA1P, "SHA1P", "01011110000mmmmm000100nnnnnddddd")
//INST(SHA1M, "SHA1M", "01011110000mmmmm001000nnnnnddddd")
INST(SHA1M, "SHA1M", "01011110000mmmmm001000nnnnnddddd")
INST(SHA1SU0, "SHA1SU0", "01011110000mmmmm001100nnnnnddddd")
//INST(SHA256H, "SHA256H", "01011110000mmmmm010000nnnnnddddd")
//INST(SHA256H2, "SHA256H2", "01011110000mmmmm010100nnnnnddddd")

11
src/frontend/A64/translate/impl/simd_sha.cpp
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@ -11,6 +11,11 @@ namespace {
IR::U32 SHAchoose(IREmitter& ir, IR::U32 x, IR::U32 y, IR::U32 z) {
return ir.Eor(ir.And(ir.Eor(y, z), x), z);
}
IR::U32 SHAmajority(IREmitter& ir, IR::U32 x, IR::U32 y, IR::U32 z) {
return ir.Or(ir.And(x, y), ir.And(ir.Or(x, y), z)) ;
}
IR::U32 SHAparity(IREmitter& ir, IR::U32 x, IR::U32 y, IR::U32 z) {
return ir.Eor(ir.Eor(y, z), x);
}
@ -50,6 +55,12 @@ bool TranslatorVisitor::SHA1C(Vec Vm, Vec Vn, Vec Vd) {
return true;
}
bool TranslatorVisitor::SHA1M(Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 result = SHA1HashUpdate(ir, Vm, Vn, Vd, SHAmajority);
ir.SetQ(Vd, result);
return true;
}
bool TranslatorVisitor::SHA1P(Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 result = SHA1HashUpdate(ir, Vm, Vn, Vd, SHAparity);
ir.SetQ(Vd, result);