thumb32: Implement AND (reg)
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MerryMage
parent
c253b8fc51
commit
158a13173c
3 changed files with 130 additions and 12 deletions
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@ -30,18 +30,13 @@
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// Data Processing (Shifted Register)
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INST(thumb32_TST_reg, "TST (reg)", "111010100001nnnn0vvv1111vvttmmmm")
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//INST(thumb32_AND_reg, "AND (reg)", "11101010000---------------------")
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//INST(thumb32_BIC_reg, "BIC (reg)", "11101010001---------------------")
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//INST(thumb32_MOV_reg, "MOV (reg)", "11101010010-1111-000----0000----")
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//INST(thumb32_LSL_imm, "LSL (imm)", "11101010010-1111----------00----")
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//INST(thumb32_LSR_imm, "LSR (imm)", "11101010010-1111----------01----")
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//INST(thumb32_ASR_imm, "ASR (imm)", "11101010010-1111----------10----")
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//INST(thumb32_RRX, "RRX", "11101010010-1111-000----0011----")
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//INST(thumb32_ROR_imm, "ROR (imm)", "11101010010-1111----------11----")
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//INST(thumb32_ORR_reg, "ORR (reg)", "11101010010---------------------")
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//INST(thumb32_MVN_reg, "MVN (reg)", "11101010011-1111----------------")
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//INST(thumb32_ORN_reg, "ORN (reg)", "11101010011---------------------")
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//INST(thumb32_TEQ_reg, "TEQ (reg)", "111010101001--------1111--------")
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INST(thumb32_AND_reg, "AND (reg)", "11101010000Snnnn0vvvddddvvttmmmm")
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INST(thumb32_BIC_reg, "BIC (reg)", "11101010001Snnnn0vvvddddvvttmmmm")
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INST(thumb32_MOV_reg, "MOV (reg)", "11101010010S11110vvvddddvvttmmmm")
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INST(thumb32_ORR_reg, "ORR (reg)", "11101010010Snnnn0vvvddddvvttmmmm")
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INST(thumb32_MVN_reg, "MVN (reg)", "11101010011S11110vvvddddvvttmmmm")
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INST(thumb32_ORN_reg, "ORN (reg)", "11101010011Snnnn0vvvddddvvttmmmm")
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INST(thumb32_TEQ_reg, "TEQ (reg)", "111010101001nnnn0vvv1111vvttmmmm")
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//INST(thumb32_EOR_reg, "EOR (reg)", "11101010100---------------------")
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//INST(thumb32_PKH, "PKH", "11101010110---------------------")
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//INST(thumb32_CMN_reg, "CMN (reg)", "111010110001--------1111--------")
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@ -21,4 +21,120 @@ bool ThumbTranslatorVisitor::thumb32_TST_reg(Reg n, Imm<3> imm3, Imm<2> imm2, Sh
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_AND_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
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ASSERT_MSG(!(d == Reg::PC && S), "Decode error");
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if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto shifted = EmitImmShift(ir.GetRegister(m), type, imm3, imm2, ir.GetCFlag());
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const auto result = ir.And(ir.GetRegister(n), shifted.result);
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ir.SetRegister(d, result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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ir.SetCFlag(shifted.carry);
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}
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_BIC_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
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if (d == Reg::PC || n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto shifted = EmitImmShift(ir.GetRegister(m), type, imm3, imm2, ir.GetCFlag());
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const auto result = ir.And(ir.GetRegister(n), ir.Not(shifted.result));
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ir.SetRegister(d, result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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ir.SetCFlag(shifted.carry);
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}
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_MOV_reg(bool S, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
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if (d == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto shifted = EmitImmShift(ir.GetRegister(m), type, imm3, imm2, ir.GetCFlag());
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const auto result = shifted.result;
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ir.SetRegister(d, result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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ir.SetCFlag(shifted.carry);
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}
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_ORR_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
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ASSERT_MSG(n != Reg::PC, "Decode error");
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if (d == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto shifted = EmitImmShift(ir.GetRegister(m), type, imm3, imm2, ir.GetCFlag());
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const auto result = ir.Or(ir.GetRegister(n), shifted.result);
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ir.SetRegister(d, result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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ir.SetCFlag(shifted.carry);
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}
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_MVN_reg(bool S, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
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if (d == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto shifted = EmitImmShift(ir.GetRegister(m), type, imm3, imm2, ir.GetCFlag());
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const auto result = ir.Not(shifted.result);
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ir.SetRegister(d, result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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ir.SetCFlag(shifted.carry);
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}
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_ORN_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
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ASSERT_MSG(n != Reg::PC, "Decode error");
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if (d == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto shifted = EmitImmShift(ir.GetRegister(m), type, imm3, imm2, ir.GetCFlag());
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const auto result = ir.Or(ir.GetRegister(n), ir.Not(shifted.result));
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ir.SetRegister(d, result);
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if (S) {
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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ir.SetCFlag(shifted.carry);
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}
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return true;
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}
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bool ThumbTranslatorVisitor::thumb32_TEQ_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftType type, Reg m) {
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if (n == Reg::PC || m == Reg::PC) {
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return UnpredictableInstruction();
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}
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const auto shifted = EmitImmShift(ir.GetRegister(m), type, imm3, imm2, ir.GetCFlag());
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const auto result = ir.Eor(ir.GetRegister(n), shifted.result);
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ir.SetNFlag(ir.MostSignificantBit(result));
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ir.SetZFlag(ir.IsZero(result));
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ir.SetCFlag(shifted.carry);
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return true;
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}
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} // namespace Dynarmic::A32
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@ -173,6 +173,13 @@ struct ThumbTranslatorVisitor final {
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// thumb32 data processing (shifted register) instructions
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bool thumb32_TST_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftType type, Reg m);
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bool thumb32_AND_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m);
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bool thumb32_BIC_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m);
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bool thumb32_MOV_reg(bool S, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m);
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bool thumb32_ORR_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m);
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bool thumb32_MVN_reg(bool S, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m);
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bool thumb32_ORN_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m);
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bool thumb32_TEQ_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftType type, Reg m);
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// thumb32 data processing (modified immediate) instructions
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bool thumb32_TST_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm8);
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