diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index aa7e4681..9f013c97 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -481,7 +481,7 @@ INST(USHR_1,                 "USHR",                                      "01111
 INST(USRA_1,                 "USRA",                                      "011111110IIIIiii000101nnnnnddddd")
 //INST(URSHR_1,                "URSHR",                                     "011111110IIIIiii001001nnnnnddddd")
 //INST(URSRA_1,                "URSRA",                                     "011111110IIIIiii001101nnnnnddddd")
-//INST(SRI_1,                  "SRI",                                       "011111110IIIIiii010001nnnnnddddd")
+INST(SRI_1,                  "SRI",                                       "011111110IIIIiii010001nnnnnddddd")
 //INST(SLI_1,                  "SLI",                                       "011111110IIIIiii010101nnnnnddddd")
 //INST(SQSHLU_1,               "SQSHLU",                                    "011111110IIIIiii011001nnnnnddddd")
 //INST(UQSHL_imm_1,            "UQSHL (immediate)",                         "011111110IIIIiii011101nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp b/src/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
index 8c2ebeb3..edffa1e1 100644
--- a/src/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
+++ b/src/frontend/A64/translate/impl/simd_scalar_shift_by_immediate.cpp
@@ -39,6 +39,25 @@ static void ShiftRight(TranslatorVisitor& v, Imm<4> immh, Imm<3> immb, Vec Vn, V
     v.V_scalar(esize, Vd, result);
 }
 
+bool TranslatorVisitor::SRI_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
+    if (!immh.Bit<3>()) {
+        return ReservedValue();
+    }
+
+    const size_t esize = 64;
+    const u8 shift_amount = static_cast<u8>((esize * 2) - concatenate(immh, immb).ZeroExtend());
+    const u64 mask = shift_amount == esize ? 0 : Common::Ones<u64>(esize) >> shift_amount;
+
+    const IR::U64 operand1 = V_scalar(esize, Vn);
+    const IR::U64 operand2 = V_scalar(esize, Vd);
+
+    const IR::U64 shifted = ir.LogicalShiftRight(operand1, ir.Imm8(shift_amount));
+    const IR::U64 result = ir.Or(ir.And(operand2, ir.Not(ir.Imm64(mask))), shifted);
+
+    V_scalar(esize, Vd, result);
+    return true;
+}
+
 bool TranslatorVisitor::SSHR_1(Imm<4> immh, Imm<3> immb, Vec Vn, Vec Vd) {
     if (!immh.Bit<3>()) {
         return ReservedValue();