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A64: Implement all half-precision variants of FCMEQ

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Lioncash 2019-05-25 01:36:39 -04:00 committed by MerryMage
parent 43fd2b400a
commit 11d1114a17
5 changed files with 44 additions and 4 deletions
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8
src/frontend/A64/decoder/a64.inc
View file

@ -382,7 +382,7 @@ INST(DUP_elt_1, "DUP (element)", "01011
// Data Processing - FP and SIMD - Scalar three // Data Processing - FP and SIMD - Scalar three
//INST(FMULX_vec_1, "FMULX", "01011110010mmmmm000111nnnnnddddd") //INST(FMULX_vec_1, "FMULX", "01011110010mmmmm000111nnnnnddddd")
INST(FMULX_vec_2, "FMULX", "010111100z1mmmmm110111nnnnnddddd") INST(FMULX_vec_2, "FMULX", "010111100z1mmmmm110111nnnnnddddd")
//INST(FCMEQ_reg_1, "FCMEQ (register)", "01011110010mmmmm001001nnnnnddddd") INST(FCMEQ_reg_1, "FCMEQ (register)", "01011110010mmmmm001001nnnnnddddd")
INST(FCMEQ_reg_2, "FCMEQ (register)", "010111100z1mmmmm111001nnnnnddddd") INST(FCMEQ_reg_2, "FCMEQ (register)", "010111100z1mmmmm111001nnnnnddddd")
INST(FRECPS_1, "FRECPS", "01011110010mmmmm001111nnnnnddddd") INST(FRECPS_1, "FRECPS", "01011110010mmmmm001111nnnnnddddd")
INST(FRECPS_2, "FRECPS", "010111100z1mmmmm111111nnnnnddddd") INST(FRECPS_2, "FRECPS", "010111100z1mmmmm111111nnnnnddddd")
@ -410,7 +410,7 @@ INST(FCVTAS_2, "FCVTAS (vector)", "01011
INST(SCVTF_int_2, "SCVTF (vector, integer)", "010111100z100001110110nnnnnddddd") INST(SCVTF_int_2, "SCVTF (vector, integer)", "010111100z100001110110nnnnnddddd")
//INST(FCMGT_zero_1, "FCMGT (zero)", "0101111011111000110010nnnnnddddd") //INST(FCMGT_zero_1, "FCMGT (zero)", "0101111011111000110010nnnnnddddd")
INST(FCMGT_zero_2, "FCMGT (zero)", "010111101z100000110010nnnnnddddd") INST(FCMGT_zero_2, "FCMGT (zero)", "010111101z100000110010nnnnnddddd")
//INST(FCMEQ_zero_1, "FCMEQ (zero)", "0101111011111000110110nnnnnddddd") INST(FCMEQ_zero_1, "FCMEQ (zero)", "0101111011111000110110nnnnnddddd")
INST(FCMEQ_zero_2, "FCMEQ (zero)", "010111101z100000110110nnnnnddddd") INST(FCMEQ_zero_2, "FCMEQ (zero)", "010111101z100000110110nnnnnddddd")
//INST(FCMLT_1, "FCMLT (zero)", "0101111011111000111010nnnnnddddd") //INST(FCMLT_1, "FCMLT (zero)", "0101111011111000111010nnnnnddddd")
INST(FCMLT_2, "FCMLT (zero)", "010111101z100000111010nnnnnddddd") INST(FCMLT_2, "FCMLT (zero)", "010111101z100000111010nnnnnddddd")
@ -574,7 +574,7 @@ INST(INS_elt, "INS (element)", "01101
// Data Processing - FP and SIMD - SIMD Three same // Data Processing - FP and SIMD - SIMD Three same
//INST(FMULX_vec_3, "FMULX", "0Q001110010mmmmm000111nnnnnddddd") //INST(FMULX_vec_3, "FMULX", "0Q001110010mmmmm000111nnnnnddddd")
//INST(FCMEQ_reg_3, "FCMEQ (register)", "0Q001110010mmmmm001001nnnnnddddd") INST(FCMEQ_reg_3, "FCMEQ (register)", "0Q001110010mmmmm001001nnnnnddddd")
INST(FRECPS_3, "FRECPS", "0Q001110010mmmmm001111nnnnnddddd") INST(FRECPS_3, "FRECPS", "0Q001110010mmmmm001111nnnnnddddd")
INST(FRSQRTS_3, "FRSQRTS", "0Q001110110mmmmm001111nnnnnddddd") INST(FRSQRTS_3, "FRSQRTS", "0Q001110110mmmmm001111nnnnnddddd")
//INST(FCMGE_reg_3, "FCMGE (register)", "0Q101110010mmmmm001001nnnnnddddd") //INST(FCMGE_reg_3, "FCMGE (register)", "0Q101110010mmmmm001001nnnnnddddd")
@ -635,7 +635,7 @@ INST(FCVTAS_4, "FCVTAS (vector)", "0Q001
INST(SCVTF_int_4, "SCVTF (vector, integer)", "0Q0011100z100001110110nnnnnddddd") INST(SCVTF_int_4, "SCVTF (vector, integer)", "0Q0011100z100001110110nnnnnddddd")
//INST(FCMGT_zero_3, "FCMGT (zero)", "0Q00111011111000110010nnnnnddddd") //INST(FCMGT_zero_3, "FCMGT (zero)", "0Q00111011111000110010nnnnnddddd")
INST(FCMGT_zero_4, "FCMGT (zero)", "0Q0011101z100000110010nnnnnddddd") INST(FCMGT_zero_4, "FCMGT (zero)", "0Q0011101z100000110010nnnnnddddd")
//INST(FCMEQ_zero_3, "FCMEQ (zero)", "0Q00111011111000110110nnnnnddddd") INST(FCMEQ_zero_3, "FCMEQ (zero)", "0Q00111011111000110110nnnnnddddd")
INST(FCMEQ_zero_4, "FCMEQ (zero)", "0Q0011101z100000110110nnnnnddddd") INST(FCMEQ_zero_4, "FCMEQ (zero)", "0Q0011101z100000110110nnnnnddddd")
//INST(FCMLT_3, "FCMLT (zero)", "0Q00111011111000111010nnnnnddddd") //INST(FCMLT_3, "FCMLT (zero)", "0Q00111011111000111010nnnnnddddd")
INST(FCMLT_4, "FCMLT (zero)", "0Q0011101z100000111010nnnnnddddd") INST(FCMLT_4, "FCMLT (zero)", "0Q0011101z100000111010nnnnnddddd")

9
src/frontend/A64/translate/impl/simd_scalar_three_same.cpp
View file

@ -346,6 +346,15 @@ bool TranslatorVisitor::FACGT_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
return ScalarFPCompareRegister(*this, sz, Vm, Vn, Vd, FPComparisonType::AbsoluteGT); return ScalarFPCompareRegister(*this, sz, Vm, Vn, Vd, FPComparisonType::AbsoluteGT);
} }
bool TranslatorVisitor::FCMEQ_reg_1(Vec Vm, Vec Vn, Vec Vd) {
const IR::U128 lhs = V(128, Vn);
const IR::U128 rhs = V(128, Vm);
const IR::U128 result = ir.FPVectorEqual(16, lhs, rhs);
V_scalar(16, Vd, ir.VectorGetElement(16, result, 0));
return true;
}
bool TranslatorVisitor::FCMEQ_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd) { bool TranslatorVisitor::FCMEQ_reg_2(bool sz, Vec Vm, Vec Vn, Vec Vd) {
return ScalarFPCompareRegister(*this, sz, Vm, Vn, Vd, FPComparisonType::EQ); return ScalarFPCompareRegister(*this, sz, Vm, Vn, Vd, FPComparisonType::EQ);
} }

9
src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp
View file

@ -100,6 +100,15 @@ bool TranslatorVisitor::ABS_1(Imm<2> size, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::FCMEQ_zero_1(Vec Vn, Vec Vd) {
const IR::U128 operand = ir.ZeroExtendToQuad(V_scalar(16, Vn));
const IR::U128 zero = ir.ZeroVector();
const IR::U128 result = ir.FPVectorEqual(16, operand, zero);
V_scalar(16, Vd, ir.VectorGetElement(16, result, 0));
return true;
}
bool TranslatorVisitor::FCMEQ_zero_2(bool sz, Vec Vn, Vec Vd) { bool TranslatorVisitor::FCMEQ_zero_2(bool sz, Vec Vn, Vec Vd) {
return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonType::EQ); return ScalarFPCompareAgainstZero(*this, sz, Vn, Vd, ComparisonType::EQ);
} }

11
src/frontend/A64/translate/impl/simd_three_same.cpp
View file

@ -740,6 +740,17 @@ bool TranslatorVisitor::FMLS_vec_2(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::FCMEQ_reg_3(bool Q, Vec Vm, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;
const IR::U128 lhs = V(datasize, Vn);
const IR::U128 rhs = V(datasize, Vm);
const IR::U128 result = ir.FPVectorEqual(16, lhs, rhs);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::FCMEQ_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) { bool TranslatorVisitor::FCMEQ_reg_4(bool Q, bool sz, Vec Vm, Vec Vn, Vec Vd) {
return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::EQ); return FPCompareRegister(*this, Q, sz, Vm, Vn, Vd, ComparisonType::EQ);
} }

11
src/frontend/A64/translate/impl/simd_two_register_misc.cpp
View file

@ -332,6 +332,17 @@ bool TranslatorVisitor::FABS_2(bool Q, bool sz, Vec Vn, Vec Vd) {
return true; return true;
} }
bool TranslatorVisitor::FCMEQ_zero_3(bool Q, Vec Vn, Vec Vd) {
const size_t datasize = Q ? 128 : 64;
const IR::U128 operand = V(datasize, Vn);
const IR::U128 zero = ir.ZeroVector();
const IR::U128 result = ir.FPVectorEqual(16, operand, zero);
V(datasize, Vd, result);
return true;
}
bool TranslatorVisitor::FCMEQ_zero_4(bool Q, bool sz, Vec Vn, Vec Vd) { bool TranslatorVisitor::FCMEQ_zero_4(bool Q, bool sz, Vec Vn, Vec Vd) {
return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonType::EQ); return FPCompareAgainstZero(*this, Q, sz, Vn, Vd, ComparisonType::EQ);
} }