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Added disassembler support for the ARM parallel add/subtract (modulo arithmetic) instructions. (#50)

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Sebastian Valle 2016-11-26 12:58:09 -05:00 committed by Merry
parent ed71e31cea
commit 11ae8d1ffa
1 changed files with 36 additions and 12 deletions
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48
src/frontend/disassembler/disassembler_arm.cpp
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@ -673,18 +673,42 @@ public:
} }
// Parallel Add/Subtract (Modulo arithmetic) instructions // Parallel Add/Subtract (Modulo arithmetic) instructions
std::string arm_SADD8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } std::string arm_SADD8(Cond cond, Reg n, Reg d, Reg m) {
std::string arm_SADD16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } return fmt::format("sadd8{} {}, {}, {}", CondToString(cond), d, n, m);
std::string arm_SASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } }
std::string arm_SSAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } std::string arm_SADD16(Cond cond, Reg n, Reg d, Reg m) {
std::string arm_SSUB8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } return fmt::format("sadd16{} {}, {}, {}", CondToString(cond), d, n, m);
std::string arm_SSUB16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } }
std::string arm_UADD8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } std::string arm_SASX(Cond cond, Reg n, Reg d, Reg m) {
std::string arm_UADD16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } return fmt::format("sasx{} {}, {}, {}", CondToString(cond), d, n, m);
std::string arm_UASX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } }
std::string arm_USAX(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } std::string arm_SSAX(Cond cond, Reg n, Reg d, Reg m) {
std::string arm_USUB8(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } return fmt::format("ssax{} {}, {}, {}", CondToString(cond), d, n, m);
std::string arm_USUB16(Cond cond, Reg n, Reg d, Reg m) { return "ice"; } }
std::string arm_SSUB8(Cond cond, Reg n, Reg d, Reg m) {
return fmt::format("ssub8{} {}, {}, {}", CondToString(cond), d, n, m);
}
std::string arm_SSUB16(Cond cond, Reg n, Reg d, Reg m) {
return fmt::format("ssub16{} {}, {}, {}", CondToString(cond), d, n, m);
}
std::string arm_UADD8(Cond cond, Reg n, Reg d, Reg m) {
return fmt::format("uadd8{} {}, {}, {}", CondToString(cond), d, n, m);
}
std::string arm_UADD16(Cond cond, Reg n, Reg d, Reg m) {
return fmt::format("uadd16{} {}, {}, {}", CondToString(cond), d, n, m);
}
std::string arm_UASX(Cond cond, Reg n, Reg d, Reg m) {
return fmt::format("uasx{} {}, {}, {}", CondToString(cond), d, n, m);
}
std::string arm_USAX(Cond cond, Reg n, Reg d, Reg m) {
return fmt::format("usax{} {}, {}, {}", CondToString(cond), d, n, m);
}
std::string arm_USUB8(Cond cond, Reg n, Reg d, Reg m) {
return fmt::format("usub8{} {}, {}, {}", CondToString(cond), d, n, m);
}
std::string arm_USUB16(Cond cond, Reg n, Reg d, Reg m) {
return fmt::format("usub16{} {}, {}, {}", CondToString(cond), d, n, m);
}
// Parallel Add/Subtract (Saturating) instructions // Parallel Add/Subtract (Saturating) instructions
std::string arm_QADD8(Cond cond, Reg n, Reg d, Reg m) { std::string arm_QADD8(Cond cond, Reg n, Reg d, Reg m) {