From 10abc77fad8e90e8b81ff96b74ec745d8b668d86 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 23 Mar 2019 13:23:31 -0400 Subject: [PATCH] A64: Handle half-precision floating point in scalar FNEG With the half-precision variant of the FPNeg opcode added, we can utilize it here to emulate the half-precision variant of FNEG. --- .../impl/floating_point_data_processing_one_register.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp b/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp index 342fd4c4..c0aff00c 100644 --- a/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp +++ b/src/frontend/A64/translate/impl/floating_point_data_processing_one_register.cpp @@ -36,12 +36,12 @@ bool TranslatorVisitor::FABS_float(Imm<2> type, Vec Vn, Vec Vd) { bool TranslatorVisitor::FNEG_float(Imm<2> type, Vec Vn, Vec Vd) { const auto datasize = FPGetDataSize(type); - if (!datasize || *datasize == 16) { + if (!datasize) { return UnallocatedEncoding(); } - const IR::U32U64 operand = V_scalar(*datasize, Vn); - const IR::U32U64 result = ir.FPNeg(operand); + const IR::U16U32U64 operand = V_scalar(*datasize, Vn); + const IR::U16U32U64 result = ir.FPNeg(operand); V_scalar(*datasize, Vd, result); return true; }