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ir: Add opcodes for performing rounding left shifts

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Lioncash 2018-08-16 11:45:12 -04:00 committed by MerryMage
parent 656ceff225
commit 0efa2ce3b0
4 changed files with 124 additions and 0 deletions
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82
src/backend_x64/emit_x64_vector.cpp
View file

@ -2326,6 +2326,88 @@ void EmitX64::EmitVectorRoundingHalvingAddU32(EmitContext& ctx, IR::Inst* inst)
EmitVectorRoundingHalvingAddUnsigned(32, ctx, inst, code);
}
template <typename T, typename U>
static void RoundingShiftLeft(VectorArray<T>& out, const VectorArray<T>& lhs, const VectorArray<U>& rhs) {
using signed_type = std::make_signed_t<T>;
using unsigned_type = std::make_unsigned_t<T>;
constexpr auto bit_size = static_cast<s64>(Common::BitSize<T>());
for (size_t i = 0; i < out.size(); i++) {
const s64 extended_shift = Common::SignExtend<8>(rhs[i] & 0xFF);
if (extended_shift >= 0) {
if (extended_shift >= bit_size) {
out[i] = 0;
} else {
out[i] = static_cast<T>(static_cast<unsigned_type>(lhs[i]) << extended_shift);
}
} else {
if ((std::is_unsigned_v<T> && extended_shift < -bit_size) ||
(std::is_signed_v<T> && extended_shift <= -bit_size)) {
out[i] = 0;
} else {
const s64 shift_value = -extended_shift - 1;
const T shifted = (lhs[i] & (static_cast<signed_type>(1) << shift_value)) >> shift_value;
if (extended_shift == -bit_size) {
out[i] = shifted;
} else {
out[i] = (lhs[i] >> -extended_shift) + shifted;
}
}
}
}
}
void EmitX64::EmitVectorRoundingShiftLeftS8(EmitContext& ctx, IR::Inst* inst) {
EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<s8>& result, const VectorArray<s8>& lhs, const VectorArray<s8>& rhs) {
RoundingShiftLeft(result, lhs, rhs);
});
}
void EmitX64::EmitVectorRoundingShiftLeftS16(EmitContext& ctx, IR::Inst* inst) {
EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<s16>& result, const VectorArray<s16>& lhs, const VectorArray<s16>& rhs) {
RoundingShiftLeft(result, lhs, rhs);
});
}
void EmitX64::EmitVectorRoundingShiftLeftS32(EmitContext& ctx, IR::Inst* inst) {
EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<s32>& result, const VectorArray<s32>& lhs, const VectorArray<s32>& rhs) {
RoundingShiftLeft(result, lhs, rhs);
});
}
void EmitX64::EmitVectorRoundingShiftLeftS64(EmitContext& ctx, IR::Inst* inst) {
EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<s64>& result, const VectorArray<s64>& lhs, const VectorArray<s64>& rhs) {
RoundingShiftLeft(result, lhs, rhs);
});
}
void EmitX64::EmitVectorRoundingShiftLeftU8(EmitContext& ctx, IR::Inst* inst) {
EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<u8>& result, const VectorArray<u8>& lhs, const VectorArray<u8>& rhs) {
RoundingShiftLeft(result, lhs, rhs);
});
}
void EmitX64::EmitVectorRoundingShiftLeftU16(EmitContext& ctx, IR::Inst* inst) {
EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<u16>& result, const VectorArray<u16>& lhs, const VectorArray<u16>& rhs) {
RoundingShiftLeft(result, lhs, rhs);
});
}
void EmitX64::EmitVectorRoundingShiftLeftU32(EmitContext& ctx, IR::Inst* inst) {
EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<u32>& result, const VectorArray<u32>& lhs, const VectorArray<u32>& rhs) {
RoundingShiftLeft(result, lhs, rhs);
});
}
void EmitX64::EmitVectorRoundingShiftLeftU64(EmitContext& ctx, IR::Inst* inst) {
EmitTwoArgumentFallback(code, ctx, inst, [](VectorArray<u64>& result, const VectorArray<u64>& lhs, const VectorArray<u64>& rhs) {
RoundingShiftLeft(result, lhs, rhs);
});
}
static void VectorShuffleImpl(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, void (Xbyak::CodeGenerator::*fn)(const Xbyak::Mmx&, const Xbyak::Operand&, u8)) {
auto args = ctx.reg_alloc.GetArgumentInfo(inst);

32
src/frontend/ir/ir_emitter.cpp
View file

@ -1424,6 +1424,38 @@ U128 IREmitter::VectorRoundingHalvingAddUnsigned(size_t esize, const U128& a, co
return {};
}
U128 IREmitter::VectorRoundingShiftLeftSigned(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorRoundingShiftLeftS8, a, b);
case 16:
return Inst<U128>(Opcode::VectorRoundingShiftLeftS16, a, b);
case 32:
return Inst<U128>(Opcode::VectorRoundingShiftLeftS32, a, b);
case 64:
return Inst<U128>(Opcode::VectorRoundingShiftLeftS64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, const U128& b) {
switch (esize) {
case 8:
return Inst<U128>(Opcode::VectorRoundingShiftLeftU8, a, b);
case 16:
return Inst<U128>(Opcode::VectorRoundingShiftLeftU16, a, b);
case 32:
return Inst<U128>(Opcode::VectorRoundingShiftLeftU32, a, b);
case 64:
return Inst<U128>(Opcode::VectorRoundingShiftLeftU64, a, b);
}
UNREACHABLE();
return {};
}
U128 IREmitter::VectorShuffleHighHalfwords(const U128& a, u8 mask) {
return Inst<U128>(Opcode::VectorShuffleHighHalfwords, a, mask);
}

2
src/frontend/ir/ir_emitter.h
View file

@ -256,6 +256,8 @@ public:
U128 VectorRotateRight(size_t esize, const U128& a, u8 amount);
U128 VectorRoundingHalvingAddSigned(size_t esize, const U128& a, const U128& b);
U128 VectorRoundingHalvingAddUnsigned(size_t esize, const U128& a, const U128& b);
U128 VectorRoundingShiftLeftSigned(size_t esize, const U128& a, const U128& b);
U128 VectorRoundingShiftLeftUnsigned(size_t esize, const U128& a, const U128& b);
U128 VectorShuffleHighHalfwords(const U128& a, u8 mask);
U128 VectorShuffleLowHalfwords(const U128& a, u8 mask);
U128 VectorShuffleWords(const U128& a, u8 mask);

8
src/frontend/ir/opcodes.inc
View file

@ -377,6 +377,14 @@ OPCODE(VectorRoundingHalvingAddS32, T::U128, T::U128,
OPCODE(VectorRoundingHalvingAddU8, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingHalvingAddU16, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingHalvingAddU32, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftS8, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftS16, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftS32, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftS64, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftU8, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftU16, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftU32, T::U128, T::U128, T::U128 )
OPCODE(VectorRoundingShiftLeftU64, T::U128, T::U128, T::U128 )
OPCODE(VectorShuffleHighHalfwords, T::U128, T::U128, T::U8 )
OPCODE(VectorShuffleLowHalfwords, T::U128, T::U128, T::U8 )
OPCODE(VectorShuffleWords, T::U128, T::U128, T::U8 )