diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index 64980928..198b6f71 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -674,7 +674,7 @@ INST(CMEQ_reg_2, "CMEQ (register)", "0Q101 INST(DUP_gen, "DUP (general)", "0Q001110000iiiii000011nnnnnddddd") INST(SMOV, "SMOV", "0Q001110000iiiii001011nnnnnddddd") INST(UMOV, "UMOV", "0Q001110000iiiii001111nnnnnddddd") -//INST(INS_gen, "INS (general)", "01001110000iiiii000111nnnnnddddd") +INST(INS_gen, "INS (general)", "01001110000iiiii000111nnnnnddddd") INST(INS_elt, "INS (element)", "01101110000iiiii0iiii1nnnnnddddd") // Data Processing - FP and SIMD - SIMD Three same diff --git a/src/frontend/A64/translate/impl/simd_copy.cpp b/src/frontend/A64/translate/impl/simd_copy.cpp index 816f9d61..6a3359f3 100644 --- a/src/frontend/A64/translate/impl/simd_copy.cpp +++ b/src/frontend/A64/translate/impl/simd_copy.cpp @@ -73,6 +73,21 @@ bool TranslatorVisitor::UMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) { return true; } +bool TranslatorVisitor::INS_gen(Imm<5> imm5, Reg Rn, Vec Vd) { + const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); + if (size > 3) return UnallocatedEncoding(); + + const size_t index = imm5.ZeroExtend() >> (size + 1); + const size_t esize = 8 << size; + const size_t datasize = 128; + + const IR::UAny element = X(esize, Rn); + const IR::U128 result = ir.VectorSetElement(esize, V(datasize, Vd), index, element); + V(datasize, Vd, result); + + return true; +} + bool TranslatorVisitor::INS_elt(Imm<5> imm5, Imm<4> imm4, Vec Vn, Vec Vd) { const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); if (size > 3) return UnallocatedEncoding();