IR: Add masked shift IR instructions
Also use these in the A64 frontend to avoid the need to mask the shift amount.
This commit is contained in:
MerryMage
parent
bd88286b21
commit
09d3c77d74
5 changed files with 161 additions and 8 deletions
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@ -4,6 +4,9 @@
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* General Public License version 2 or any later version.
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*/
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#include <cstddef>
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#include <type_traits>
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#include "backend/x64/block_of_code.h"
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#include "backend/x64/emit_x64.h"
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#include "common/assert.h"
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@ -725,6 +728,112 @@ void EmitX64::EmitRotateRightExtended(EmitContext& ctx, IR::Inst* inst) {
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ctx.reg_alloc.DefineValue(inst, result);
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}
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template <typename ShfitFT, typename BMI2FT>
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static void EmitMaskedShift32(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, ShfitFT shift_fn, [[maybe_unused]] BMI2FT bmi2_shift) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto& operand_arg = args[0];
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auto& shift_arg = args[1];
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if (shift_arg.IsImmediate()) {
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const Xbyak::Reg32 result = ctx.reg_alloc.UseScratchGpr(operand_arg).cvt32();
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const u8 shift = shift_arg.GetImmediateU8();
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shift_fn(result, shift & 0x1F);
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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if constexpr (!std::is_same_v<BMI2FT, std::nullptr_t>) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tBMI2)) {
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const Xbyak::Reg32 result = ctx.reg_alloc.ScratchGpr().cvt32();
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const Xbyak::Reg32 operand = ctx.reg_alloc.UseGpr(operand_arg).cvt32();
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const Xbyak::Reg32 shift = ctx.reg_alloc.UseGpr(shift_arg).cvt32();
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(code.*bmi2_shift)(result, operand, shift);
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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}
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ctx.reg_alloc.Use(shift_arg, HostLoc::RCX);
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const Xbyak::Reg32 result = ctx.reg_alloc.UseScratchGpr(operand_arg).cvt32();
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shift_fn(result, code.cl);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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template <typename ShfitFT, typename BMI2FT>
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static void EmitMaskedShift64(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, ShfitFT shift_fn, [[maybe_unused]] BMI2FT bmi2_shift) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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auto& operand_arg = args[0];
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auto& shift_arg = args[1];
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if (shift_arg.IsImmediate()) {
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const Xbyak::Reg64 result = ctx.reg_alloc.UseScratchGpr(operand_arg);
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const u8 shift = shift_arg.GetImmediateU8();
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shift_fn(result, shift & 0x3F);
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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if constexpr (!std::is_same_v<BMI2FT, std::nullptr_t>) {
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tBMI2)) {
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const Xbyak::Reg64 result = ctx.reg_alloc.ScratchGpr();
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const Xbyak::Reg64 operand = ctx.reg_alloc.UseGpr(operand_arg);
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const Xbyak::Reg64 shift = ctx.reg_alloc.UseGpr(shift_arg);
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(code.*bmi2_shift)(result, operand, shift);
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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}
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ctx.reg_alloc.Use(shift_arg, HostLoc::RCX);
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const Xbyak::Reg64 result = ctx.reg_alloc.UseScratchGpr(operand_arg);
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shift_fn(result, code.cl);
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ctx.reg_alloc.DefineValue(inst, result);
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}
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void EmitX64::EmitLogicalShiftLeftMasked32(EmitContext& ctx, IR::Inst* inst) {
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EmitMaskedShift32(code, ctx, inst, [&](auto result, auto shift) { code.shl(result, shift); }, &Xbyak::CodeGenerator::shlx);
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}
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void EmitX64::EmitLogicalShiftLeftMasked64(EmitContext& ctx, IR::Inst* inst) {
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EmitMaskedShift64(code, ctx, inst, [&](auto result, auto shift) { code.shl(result, shift); }, &Xbyak::CodeGenerator::shlx);
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}
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void EmitX64::EmitLogicalShiftRightMasked32(EmitContext& ctx, IR::Inst* inst) {
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EmitMaskedShift32(code, ctx, inst, [&](auto result, auto shift) { code.shr(result, shift); }, &Xbyak::CodeGenerator::shrx);
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}
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void EmitX64::EmitLogicalShiftRightMasked64(EmitContext& ctx, IR::Inst* inst) {
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EmitMaskedShift64(code, ctx, inst, [&](auto result, auto shift) { code.shr(result, shift); }, &Xbyak::CodeGenerator::shrx);
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}
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void EmitX64::EmitArithmeticShiftRightMasked32(EmitContext& ctx, IR::Inst* inst) {
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EmitMaskedShift32(code, ctx, inst, [&](auto result, auto shift) { code.sar(result, shift); }, &Xbyak::CodeGenerator::sarx);
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}
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void EmitX64::EmitArithmeticShiftRightMasked64(EmitContext& ctx, IR::Inst* inst) {
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EmitMaskedShift64(code, ctx, inst, [&](auto result, auto shift) { code.sar(result, shift); }, &Xbyak::CodeGenerator::sarx);
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}
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void EmitX64::EmitRotateRightMasked32(EmitContext& ctx, IR::Inst* inst) {
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EmitMaskedShift32(code, ctx, inst, [&](auto result, auto shift) { code.ror(result, shift); }, nullptr);
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}
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void EmitX64::EmitRotateRightMasked64(EmitContext& ctx, IR::Inst* inst) {
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EmitMaskedShift64(code, ctx, inst, [&](auto result, auto shift) { code.ror(result, shift); }, nullptr);
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}
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static Xbyak::Reg8 DoCarry(RegAlloc& reg_alloc, Argument& carry_in, IR::Inst* carry_out) {
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if (carry_in.IsImmediate()) {
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return carry_out ? reg_alloc.ScratchGpr().cvt8() : Xbyak::Reg8{-1};
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@ -8,17 +8,13 @@
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namespace Dynarmic::A64 {
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static IR::U8 SanitizeShiftAmount(TranslatorVisitor& v, size_t datasize, const IR::U32U64& amount) {
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return v.ir.LeastSignificantByte(v.ir.And(amount, v.I(datasize, datasize - 1)));
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}
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bool TranslatorVisitor::LSLV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
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const size_t datasize = sf ? 64 : 32;
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const IR::U32U64 operand = X(datasize, Rn);
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const IR::U32U64 shift_amount = X(datasize, Rm);
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const IR::U32U64 result = ir.LogicalShiftLeft(operand, SanitizeShiftAmount(*this, datasize, shift_amount));
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const IR::U32U64 result = ir.LogicalShiftLeftMasked(operand, shift_amount);
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X(datasize, Rd, result);
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return true;
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@ -30,7 +26,7 @@ bool TranslatorVisitor::LSRV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
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const IR::U32U64 operand = X(datasize, Rn);
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const IR::U32U64 shift_amount = X(datasize, Rm);
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const IR::U32U64 result = ir.LogicalShiftRight(operand, SanitizeShiftAmount(*this, datasize, shift_amount));
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const IR::U32U64 result = ir.LogicalShiftRightMasked(operand, shift_amount);
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X(datasize, Rd, result);
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return true;
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@ -42,7 +38,7 @@ bool TranslatorVisitor::ASRV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
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const IR::U32U64 operand = X(datasize, Rn);
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const IR::U32U64 shift_amount = X(datasize, Rm);
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const IR::U32U64 result = ir.ArithmeticShiftRight(operand, SanitizeShiftAmount(*this, datasize, shift_amount));
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const IR::U32U64 result = ir.ArithmeticShiftRightMasked(operand, shift_amount);
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X(datasize, Rd, result);
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return true;
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@ -54,7 +50,7 @@ bool TranslatorVisitor::RORV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
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const IR::U32U64 operand = X(datasize, Rn);
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const IR::U32U64 shift_amount = X(datasize, Rm);
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const IR::U32U64 result = ir.RotateRight(operand, SanitizeShiftAmount(*this, datasize, shift_amount));
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const IR::U32U64 result = ir.RotateRightMasked(operand, shift_amount);
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X(datasize, Rd, result);
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return true;
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@ -185,6 +185,42 @@ U32U64 IREmitter::RotateRight(const U32U64& value_in, const U8& shift_amount) {
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}
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}
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U32U64 IREmitter::LogicalShiftLeftMasked(const U32U64& value_in, const U32U64& shift_amount) {
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ASSERT(value_in.GetType() == shift_amount.GetType());
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if (value_in.GetType() == Type::U32) {
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return Inst<U32>(Opcode::LogicalShiftLeftMasked32, value_in, shift_amount);
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} else {
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return Inst<U64>(Opcode::LogicalShiftLeftMasked64, value_in, shift_amount);
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}
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}
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U32U64 IREmitter::LogicalShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount) {
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ASSERT(value_in.GetType() == shift_amount.GetType());
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if (value_in.GetType() == Type::U32) {
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return Inst<U32>(Opcode::LogicalShiftRightMasked32, value_in, shift_amount);
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} else {
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return Inst<U64>(Opcode::LogicalShiftRightMasked64, value_in, shift_amount);
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}
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}
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U32U64 IREmitter::ArithmeticShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount) {
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ASSERT(value_in.GetType() == shift_amount.GetType());
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if (value_in.GetType() == Type::U32) {
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return Inst<U32>(Opcode::ArithmeticShiftRightMasked32, value_in, shift_amount);
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} else {
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return Inst<U64>(Opcode::ArithmeticShiftRightMasked64, value_in, shift_amount);
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}
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}
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U32U64 IREmitter::RotateRightMasked(const U32U64& value_in, const U32U64& shift_amount) {
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ASSERT(value_in.GetType() == shift_amount.GetType());
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if (value_in.GetType() == Type::U32) {
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return Inst<U32>(Opcode::RotateRightMasked32, value_in, shift_amount);
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} else {
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return Inst<U64>(Opcode::RotateRightMasked64, value_in, shift_amount);
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}
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}
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ResultAndCarryAndOverflow<U32> IREmitter::AddWithCarry(const U32& a, const U32& b, const U1& carry_in) {
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const auto result = Inst<U32>(Opcode::Add32, a, b, carry_in);
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const auto carry_out = Inst<U1>(Opcode::GetCarryFromOp, result);
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@ -114,6 +114,10 @@ public:
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U32U64 LogicalShiftRight(const U32U64& value_in, const U8& shift_amount);
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U32U64 ArithmeticShiftRight(const U32U64& value_in, const U8& shift_amount);
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U32U64 RotateRight(const U32U64& value_in, const U8& shift_amount);
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U32U64 LogicalShiftLeftMasked(const U32U64& value_in, const U32U64& shift_amount);
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U32U64 LogicalShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount);
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U32U64 ArithmeticShiftRightMasked(const U32U64& value_in, const U32U64& shift_amount);
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U32U64 RotateRightMasked(const U32U64& value_in, const U32U64& shift_amount);
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ResultAndCarry<U32> RotateRightExtended(const U32& value_in, const U1& carry_in);
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ResultAndCarryAndOverflow<U32> AddWithCarry(const U32& a, const U32& b, const U1& carry_in);
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ResultAndCarryAndOverflow<U32> SubWithCarry(const U32& a, const U32& b, const U1& carry_in);
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@ -113,6 +113,14 @@ OPCODE(ArithmeticShiftRight64, U64, U64,
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OPCODE(RotateRight32, U32, U32, U8, U1 )
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OPCODE(RotateRight64, U64, U64, U8 )
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OPCODE(RotateRightExtended, U32, U32, U1 )
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OPCODE(LogicalShiftLeftMasked32, U32, U32, U32 )
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OPCODE(LogicalShiftLeftMasked64, U64, U64, U64 )
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OPCODE(LogicalShiftRightMasked32, U32, U32, U32 )
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OPCODE(LogicalShiftRightMasked64, U64, U64, U64 )
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OPCODE(ArithmeticShiftRightMasked32, U32, U32, U32 )
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OPCODE(ArithmeticShiftRightMasked64, U64, U64, U64 )
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OPCODE(RotateRightMasked32, U32, U32, U32 )
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OPCODE(RotateRightMasked64, U64, U64, U64 )
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OPCODE(Add32, U32, U32, U32, U1 )
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OPCODE(Add64, U64, U64, U64, U1 )
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OPCODE(Sub32, U32, U32, U32, U1 )
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