emit_x64_floating_point: Reduce NaN processing overhead
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MerryMage
parent
f5e11d117a
commit
07e0585994
1 changed files with 260 additions and 86 deletions
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@ -207,6 +207,152 @@ Xbyak::Label ProcessNaN(BlockOfCode& code, Xbyak::Xmm a) {
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return end;
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}
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// This is necessary because x86 and ARM differ in they way they return NaNs from floating point operations
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//
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// ARM behaviour:
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// op1 op2 result
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// SNaN SNaN/QNaN op1
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// QNaN SNaN op2
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// QNaN QNaN op1
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// SNaN/QNaN other op1
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// other SNaN/QNaN op2
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//
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// x86 behaviour:
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// op1 op2 result
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// SNaN/QNaN SNaN/QNaN op1
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// SNaN/QNaN other op1
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// other SNaN/QNaN op2
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//
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// With ARM: SNaNs take priority. With x86: it doesn't matter.
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//
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// From the above we can see what differs between the architectures is
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// the case when op1 == QNaN and op2 == SNaN.
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//
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// We assume that registers op1 and op2 are read-only. This function also trashes xmm0.
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// We allow for the case where op1 and result are the same register. We do not read from op1 once result is written to.
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template<size_t fsize>
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void EmitPostProcessNaNs(BlockOfCode& code, Xbyak::Xmm result, Xbyak::Xmm op1, Xbyak::Xmm op2, Xbyak::Reg64 tmp, Xbyak::Label end) {
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using FPT = mp::unsigned_integer_of_size<fsize>;
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constexpr FPT exponent_mask = FP::FPInfo<FPT>::exponent_mask;
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constexpr FPT mantissa_msb = FP::FPInfo<FPT>::mantissa_msb;
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constexpr u8 mantissa_msb_bit = static_cast<u8>(FP::FPInfo<FPT>::explicit_mantissa_width - 1);
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// At this point we know that at least one of op1 and op2 is a NaN.
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// Thus in op1 ^ op2 at least one of the two would have all 1 bits in the exponent.
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// Keeping in mind xor is commutative, there are only four cases:
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// SNaN ^ SNaN/Inf -> exponent == 0, mantissa_msb == 0
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// QNaN ^ QNaN -> exponent == 0, mantissa_msb == 0
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// QNaN ^ SNaN/Inf -> exponent == 0, mantissa_msb == 1
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// SNaN/QNaN ^ Otherwise -> exponent != 0, mantissa_msb == ?
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//
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// We're only really interested in op1 == QNaN and op2 == SNaN,
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// so we filter out everything else.
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//
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// We do it this way instead of checking that op1 is QNaN because
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// op1 == QNaN && op2 == QNaN is the most common case. With this method
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// that case would only require one branch.
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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code.vxorps(xmm0, op1, op2);
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} else {
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code.movaps(xmm0, op1);
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code.xorps(xmm0, op2);
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}
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constexpr size_t shift = fsize == 32 ? 0 : 48;
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if constexpr (fsize == 32) {
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code.movd(tmp.cvt32(), xmm0);
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} else {
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// We do this to avoid requiring 64-bit immediates
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code.pextrw(tmp.cvt32(), xmm0, shift / 16);
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}
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code.and_(tmp.cvt32(), static_cast<u32>((exponent_mask | mantissa_msb) >> shift));
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code.cmp(tmp.cvt32(), static_cast<u32>(mantissa_msb >> shift));
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code.jne(end, code.T_NEAR);
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// If we're here there are four cases left:
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// op1 == SNaN && op2 == QNaN
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// op1 == Inf && op2 == QNaN
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// op1 == QNaN && op2 == SNaN <<< The problematic case
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// op1 == QNaN && op2 == Inf
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if constexpr (fsize == 32) {
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code.movd(tmp.cvt32(), op2);
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code.shl(tmp.cvt32(), 32 - mantissa_msb_bit);
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} else {
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code.movq(tmp, op2);
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code.shl(tmp, 64 - mantissa_msb_bit);
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}
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// If op2 is a SNaN, CF = 0 and ZF = 0.
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code.jna(end, code.T_NEAR);
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// Silence the SNaN as required by spec.
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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code.vorps(result, op2, code.MConst(xword, mantissa_msb));
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} else {
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code.movaps(result, op2);
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code.orps(result, code.MConst(xword, mantissa_msb));
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}
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code.jmp(end, code.T_NEAR);
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}
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// Do full NaN processing.
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template<size_t fsize>
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void EmitProcessNaNs(BlockOfCode& code, Xbyak::Xmm result, Xbyak::Xmm op1, Xbyak::Xmm op2, Xbyak::Reg64 tmp, Xbyak::Label end) {
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using FPT = mp::unsigned_integer_of_size<fsize>;
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constexpr FPT exponent_mask = FP::FPInfo<FPT>::exponent_mask;
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constexpr FPT mantissa_msb = FP::FPInfo<FPT>::mantissa_msb;
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constexpr u8 mantissa_msb_bit = static_cast<u8>(FP::FPInfo<FPT>::explicit_mantissa_width - 1);
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Xbyak::Label return_sum;
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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code.vxorps(xmm0, op1, op2);
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} else {
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code.movaps(xmm0, op1);
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code.xorps(xmm0, op2);
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}
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constexpr size_t shift = fsize == 32 ? 0 : 48;
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if constexpr (fsize == 32) {
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code.movd(tmp.cvt32(), xmm0);
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} else {
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code.pextrw(tmp.cvt32(), xmm0, shift / 16);
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}
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code.and_(tmp.cvt32(), static_cast<u32>((exponent_mask | mantissa_msb) >> shift));
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code.cmp(tmp.cvt32(), static_cast<u32>(mantissa_msb >> shift));
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code.jne(return_sum);
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if constexpr (fsize == 32) {
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code.movd(tmp.cvt32(), op2);
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code.shl(tmp.cvt32(), 32 - mantissa_msb_bit);
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} else {
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code.movq(tmp, op2);
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code.shl(tmp, 64 - mantissa_msb_bit);
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}
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code.jna(return_sum);
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if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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code.vorps(result, op2, code.MConst(xword, mantissa_msb));
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} else {
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code.movaps(result, op2);
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code.orps(result, code.MConst(xword, mantissa_msb));
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}
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code.jmp(end, code.T_NEAR);
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// x86 behaviour is reliable in this case
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code.L(return_sum);
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if (result == op1) {
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FCODE(adds)(result, op2);
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} else if (code.DoesCpuSupport(Xbyak::util::Cpu::tAVX)) {
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FCODE(vadds)(result, op1, op2);
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} else {
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code.movaps(result, op1);
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FCODE(adds)(result, op2);
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}
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code.jmp(end, code.T_NEAR);
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}
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template <size_t fsize, typename Function>
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void FPTwoOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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@ -274,8 +420,58 @@ void FPThreeOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, [[maybe_unus
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}
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template <size_t fsize, typename Function>
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void FPThreeOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn, CallDenormalsAreZero call_denormals_are_zero = CallDenormalsAreZero::No) {
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FPThreeOp<fsize>(code, ctx, inst, nullptr, fn, call_denormals_are_zero);
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void FPThreeOp(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst, Function fn) {
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using FPT = mp::unsigned_integer_of_size<fsize>;
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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if (ctx.FPSCR_DN() || !ctx.AccurateNaN()) {
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm operand = ctx.reg_alloc.UseScratchXmm(args[1]);
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if constexpr (std::is_member_function_pointer_v<Function>) {
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(code.*fn)(result, operand);
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} else {
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fn(result, operand);
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}
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if (ctx.AccurateNaN()) {
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ForceToDefaultNaN<fsize>(code, result);
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}
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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const Xbyak::Xmm op1 = ctx.reg_alloc.UseXmm(args[0]);
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const Xbyak::Xmm op2 = ctx.reg_alloc.UseXmm(args[1]);
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const Xbyak::Xmm result = ctx.reg_alloc.ScratchXmm();
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const Xbyak::Reg64 tmp = ctx.reg_alloc.ScratchGpr();
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Xbyak::Label end, nan, op_are_nans;
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code.movaps(result, op1);
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if constexpr (std::is_member_function_pointer_v<Function>) {
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(code.*fn)(result, op2);
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} else {
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fn(result, op2);
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}
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FCODE(ucomis)(result, result);
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code.jp(nan, code.T_NEAR);
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code.L(end);
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code.SwitchToFarCode();
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code.L(nan);
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FCODE(ucomis)(op1, op2);
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code.jp(op_are_nans);
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// Here we must return a positive NaN, because the indefinite value on x86 is a negative NaN!
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code.movaps(result, code.MConst(xword, FP::FPInfo<FPT>::DefaultNaN()));
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code.jmp(end, code.T_NEAR);
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code.L(op_are_nans);
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EmitPostProcessNaNs<fsize>(code, result, op1, op2, tmp, end);
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code.SwitchToNearCode();
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ctx.reg_alloc.DefineValue(inst, result);
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}
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} // anonymous namespace
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@ -334,14 +530,13 @@ void EmitX64::EmitFPDiv64(EmitContext& ctx, IR::Inst* inst) {
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template<size_t fsize>
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static void EmitFPMax(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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if (ctx.FPSCR_DN()) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm operand = ctx.reg_alloc.UseScratchXmm(args[1]);
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const Xbyak::Reg64 gpr_scratch = ctx.reg_alloc.ScratchGpr();
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if (ctx.FPSCR_FTZ()) {
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const Xbyak::Reg64 gpr_scratch = ctx.reg_alloc.ScratchGpr();
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DenormalsAreZero<fsize>(code, result, gpr_scratch);
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DenormalsAreZero<fsize>(code, operand, gpr_scratch);
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}
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@ -361,26 +556,16 @@ static void EmitFPMax(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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code.jmp(end);
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code.L(nan);
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if (ctx.FPSCR_DN() || !ctx.AccurateNaN()) {
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code.movaps(result, code.MConst(xword, fsize == 32 ? f32_nan : f64_nan));
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code.jmp(end);
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} else {
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EmitProcessNaNs<fsize>(code, result, result, operand, gpr_scratch, end);
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}
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code.SwitchToNearCode();
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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FPThreeOp<fsize>(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand){
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Xbyak::Label equal, end;
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FCODE(ucomis)(result, operand);
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code.jz(equal);
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FCODE(maxs)(result, operand);
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code.jmp(end);
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code.L(equal);
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code.andps(result, operand);
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code.L(end);
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}, CallDenormalsAreZero::Yes);
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}
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void EmitX64::EmitFPMax32(EmitContext& ctx, IR::Inst* inst) {
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@ -461,14 +646,13 @@ void EmitX64::EmitFPMaxNumeric64(EmitContext& ctx, IR::Inst* inst) {
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template<size_t fsize>
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static void EmitFPMin(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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if (ctx.FPSCR_DN()) {
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auto args = ctx.reg_alloc.GetArgumentInfo(inst);
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const Xbyak::Xmm result = ctx.reg_alloc.UseScratchXmm(args[0]);
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const Xbyak::Xmm operand = ctx.reg_alloc.UseScratchXmm(args[1]);
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const Xbyak::Reg64 gpr_scratch = ctx.reg_alloc.ScratchGpr();
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if (ctx.FPSCR_FTZ()) {
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const Xbyak::Reg64 gpr_scratch = ctx.reg_alloc.ScratchGpr();
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DenormalsAreZero<fsize>(code, result, gpr_scratch);
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DenormalsAreZero<fsize>(code, operand, gpr_scratch);
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}
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@ -488,26 +672,16 @@ static void EmitFPMin(BlockOfCode& code, EmitContext& ctx, IR::Inst* inst) {
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code.jmp(end);
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code.L(nan);
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if (ctx.FPSCR_DN()) {
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code.movaps(result, code.MConst(xword, fsize == 32 ? f32_nan : f64_nan));
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code.jmp(end);
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} else {
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EmitProcessNaNs<fsize>(code, result, result, operand, gpr_scratch, end);
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}
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code.SwitchToNearCode();
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ctx.reg_alloc.DefineValue(inst, result);
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return;
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}
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FPThreeOp<fsize>(code, ctx, inst, [&](Xbyak::Xmm result, Xbyak::Xmm operand){
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Xbyak::Label equal, end;
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FCODE(ucomis)(result, operand);
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code.jz(equal);
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FCODE(mins)(result, operand);
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code.jmp(end);
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code.L(equal);
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code.orps(result, operand);
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code.L(end);
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}, CallDenormalsAreZero::Yes);
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}
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void EmitX64::EmitFPMin32(EmitContext& ctx, IR::Inst* inst) {
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