thumb32: Add Rn argument to ADD/SUB (Plain Binary Immediate)

This commit is contained in:
MerryMage 2021-05-05 11:37:15 +01:00
parent ebe44dab7a
commit 075fdeaee0
3 changed files with 12 additions and 12 deletions

View file

@ -67,10 +67,10 @@ INST(thumb32_RSB_imm, "RSB (imm)", "11110v01110Snnnn0vvvdd
// Data Processing (Plain Binary Immediate)
INST(thumb32_ADR_t3, "ADR", "11110i10000011110iiiddddiiiiiiii")
INST(thumb32_ADD_imm_2, "ADD (imm)", "11110i10000011010iiiddddiiiiiiii")
INST(thumb32_ADD_imm_2, "ADD (imm)", "11110i100000nnnn0iiiddddiiiiiiii")
INST(thumb32_MOVW_imm, "MOVW (imm)", "11110i100100iiii0iiiddddiiiiiiii")
INST(thumb32_ADR_t2, "ADR", "11110i10101011110iiiddddiiiiiiii")
INST(thumb32_SUB_imm_2, "SUB (imm)", "11110i10101011010iiiddddiiiiiiii")
INST(thumb32_SUB_imm_2, "SUB (imm)", "11110i101010nnnn0iiiddddiiiiiiii")
INST(thumb32_MOVT, "MOVT", "11110i101100iiii0iiiddddiiiiiiii")
INST(thumb32_UDF, "Invalid decoding", "11110011-010----0000----0001----")
INST(thumb32_SSAT16, "SSAT16", "111100110010nnnn0000dddd0000iiii")

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@ -77,14 +77,14 @@ bool TranslatorVisitor::thumb32_ADR_t3(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> i
return true;
}
bool TranslatorVisitor::thumb32_ADD_imm_2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8) {
if (d == Reg::PC) {
bool TranslatorVisitor::thumb32_ADD_imm_2(Imm<1> imm1, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
if (d == Reg::PC || n == Reg::PC) {
return UnpredictableInstruction();
}
const u32 imm = concatenate(imm1, imm3, imm8).ZeroExtend();
const auto sp = ir.GetRegister(Reg::SP);
const auto result = ir.AddWithCarry(sp, ir.Imm32(imm), ir.Imm1(0));
const auto reg_n = ir.GetRegister(n);
const auto result = ir.AddWithCarry(reg_n, ir.Imm32(imm), ir.Imm1(0));
ir.SetRegister(d, result.result);
return true;
@ -188,14 +188,14 @@ bool TranslatorVisitor::thumb32_SSAT16(Reg n, Reg d, Imm<4> sat_imm) {
return Saturation16(*this, n, d, sat_imm.ZeroExtend() + 1, &IREmitter::SignedSaturation);
}
bool TranslatorVisitor::thumb32_SUB_imm_2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8) {
if (d == Reg::PC) {
bool TranslatorVisitor::thumb32_SUB_imm_2(Imm<1> imm1, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
if (d == Reg::PC || n == Reg::PC) {
return UnpredictableInstruction();
}
const u32 imm = concatenate(imm1, imm3, imm8).ZeroExtend();
const auto sp = ir.GetRegister(Reg::SP);
const auto result = ir.SubWithCarry(sp, ir.Imm32(imm), ir.Imm1(1));
const auto reg_n = ir.GetRegister(n);
const auto result = ir.SubWithCarry(reg_n, ir.Imm32(imm), ir.Imm1(1));
ir.SetRegister(d, result.result);
return true;

View file

@ -549,7 +549,7 @@ struct TranslatorVisitor final {
// thumb32 data processing (plain binary immediate) instructions.
bool thumb32_ADR_t2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_ADR_t3(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_ADD_imm_2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_ADD_imm_2(Imm<1> imm1, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_BFC(Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb);
bool thumb32_BFI(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> msb);
bool thumb32_MOVT(Imm<1> imm1, Imm<4> imm4, Imm<3> imm3, Reg d, Imm<8> imm8);
@ -557,7 +557,7 @@ struct TranslatorVisitor final {
bool thumb32_SBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> widthm1);
bool thumb32_SSAT(bool sh, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> sat_imm);
bool thumb32_SSAT16(Reg n, Reg d, Imm<4> sat_imm);
bool thumb32_SUB_imm_2(Imm<1> imm1, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_SUB_imm_2(Imm<1> imm1, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8);
bool thumb32_UBFX(Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> widthm1);
bool thumb32_USAT(bool sh, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, Imm<5> sat_imm);
bool thumb32_USAT16(Reg n, Reg d, Imm<4> sat_imm);