diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc
index 5612c790..f630bb98 100644
--- a/src/frontend/A64/decoder/a64.inc
+++ b/src/frontend/A64/decoder/a64.inc
@@ -672,7 +672,7 @@ INST(CMEQ_reg_2,             "CMEQ (register)",                           "0Q101
 
 // Data Processing - FP and SIMD - SIMD Copy
 INST(DUP_gen,                "DUP (general)",                             "0Q001110000iiiii000011nnnnnddddd")
-//INST(SMOV,                   "SMOV",                                      "0Q001110000iiiii001011nnnnnddddd")
+INST(SMOV,                   "SMOV",                                      "0Q001110000iiiii001011nnnnnddddd")
 INST(UMOV,                   "UMOV",                                      "0Q001110000iiiii001111nnnnnddddd")
 //INST(INS_gen,                "INS (general)",                             "01001110000iiiii000111nnnnnddddd")
 //INST(INS_elt,                "INS (element)",                             "01101110000iiiii0iiii1nnnnnddddd")
diff --git a/src/frontend/A64/translate/impl/simd_copy.cpp b/src/frontend/A64/translate/impl/simd_copy.cpp
index b806da00..415e6861 100644
--- a/src/frontend/A64/translate/impl/simd_copy.cpp
+++ b/src/frontend/A64/translate/impl/simd_copy.cpp
@@ -36,6 +36,24 @@ bool TranslatorVisitor::DUP_gen(bool Q, Imm<5> imm5, Reg Rn, Vec Vd) {
     return true;
 }
 
+bool TranslatorVisitor::SMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) {
+    const size_t size = Common::LowestSetBit(imm5.ZeroExtend());
+    if (size == 2 && !Q) return UnallocatedEncoding();
+    if (size > 2) return UnallocatedEncoding();
+
+    const size_t idxdsize = imm5.Bit<4>() ? 128 : 64;
+    const size_t index = imm5.ZeroExtend<size_t>() >> (size + 1);
+    const size_t esize = 8 << size;
+    const size_t datasize = Q ? 64 : 32;
+
+    const IR::U128 operand = V(idxdsize, Vn);
+
+    const IR::UAny elem = ir.VectorGetElement(esize, operand, index);
+    X(datasize, Rd, SignExtend(elem, datasize));
+
+    return true;
+}
+
 bool TranslatorVisitor::UMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) {
     const size_t size = Common::LowestSetBit(imm5.ZeroExtend());
     if (size < 3 && Q) return UnallocatedEncoding();