From 0441ab81a162ffffb96ab5021f443c281a62e2d9 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Sat, 16 May 2020 11:31:17 -0400
Subject: [PATCH] A32: Implement ASIMD VAND (register)

---
 src/CMakeLists.txt                            |  1 +
 src/frontend/A32/decoder/asimd.inc            |  2 +-
 .../A32/translate/impl/asimd_three_same.cpp   | 35 +++++++++++++++++++
 .../A32/translate/impl/translate_arm.h        |  3 ++
 4 files changed, 40 insertions(+), 1 deletion(-)
 create mode 100644 src/frontend/A32/translate/impl/asimd_three_same.cpp

diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index b44cb85e..3e47ce00 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -123,6 +123,7 @@ if ("A32" IN_LIST DYNARMIC_FRONTENDS)
         frontend/A32/location_descriptor.h
         frontend/A32/PSR.h
         frontend/A32/translate/impl/asimd_load_store_structures.cpp
+        frontend/A32/translate/impl/asimd_three_same.cpp
         frontend/A32/translate/impl/barrier.cpp
         frontend/A32/translate/impl/branch.cpp
         frontend/A32/translate/impl/coprocessor.cpp
diff --git a/src/frontend/A32/decoder/asimd.inc b/src/frontend/A32/decoder/asimd.inc
index 8be4528f..d6bf31b5 100644
--- a/src/frontend/A32/decoder/asimd.inc
+++ b/src/frontend/A32/decoder/asimd.inc
@@ -2,7 +2,7 @@
 //INST(asimd_VHADD,           "VHADD",                    "1111001U0-CC--------0000---0----") // ASIMD
 //INST(asimd_VQADD,           "VQADD",                    "1111001U0-CC--------0000---1----") // ASIMD
 //INST(asimd_VRHADD,          "VRHADD",                   "1111001U0-CC--------0001---0----") // ASIMD
-//INST(asimd_VAND_reg,        "VAND (register)",          "111100100-00--------0001---1----") // ASIMD
+INST(asimd_VAND_reg,        "VAND (register)",          "111100100D00nnnndddd0001NQM1mmmm") // ASIMD
 //INST(asimd_VBIC_reg,        "VBIC (register)",          "111100100-01--------0001---1----") // ASIMD
 //INST(asimd_VORR_reg,        "VORR (register)",          "111100100-10--------0001---1----") // ASIMD
 //INST(asimd_VORN_reg,        "VORN (register)",          "111100100-11--------0001---1----") // ASIMD
diff --git a/src/frontend/A32/translate/impl/asimd_three_same.cpp b/src/frontend/A32/translate/impl/asimd_three_same.cpp
new file mode 100644
index 00000000..d54b6c69
--- /dev/null
+++ b/src/frontend/A32/translate/impl/asimd_three_same.cpp
@@ -0,0 +1,35 @@
+/* This file is part of the dynarmic project.
+ * Copyright (c) 2020 MerryMage
+ * SPDX-License-Identifier: 0BSD
+ */
+
+#include "common/bit_util.h"
+
+#include "frontend/A32/translate/impl/translate_arm.h"
+
+namespace Dynarmic::A32 {
+static ExtReg ToExtReg(size_t base, bool bit) {
+    return ExtReg::D0 + (base + (bit ? 16 : 0));
+}
+
+bool ArmTranslatorVisitor::asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
+    if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
+        return UndefinedInstruction();
+    }
+
+    const auto d = ToExtReg(Vd, D);
+    const auto m = ToExtReg(Vm, M);
+    const auto n = ToExtReg(Vn, N);
+    const size_t regs = Q ? 2 : 1;
+
+    for (size_t i = 0; i < regs; i++) {
+        const IR::U32U64 reg_m = ir.GetExtendedRegister(m + i);
+        const IR::U32U64 reg_n = ir.GetExtendedRegister(n + i);
+        const IR::U32U64 result = ir.And(reg_n, reg_m);
+        ir.SetExtendedRegister(d + i, result);
+    }
+
+    return true;
+}
+
+} // namespace Dynarmic::A32
diff --git a/src/frontend/A32/translate/impl/translate_arm.h b/src/frontend/A32/translate/impl/translate_arm.h
index 5851a3fa..db70e370 100644
--- a/src/frontend/A32/translate/impl/translate_arm.h
+++ b/src/frontend/A32/translate/impl/translate_arm.h
@@ -429,6 +429,9 @@ struct ArmTranslatorVisitor final {
     bool vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8);
     bool vfp_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8);
 
+    // Advanced SIMD three register variants
+    bool asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm);
+
     // Advanced SIMD load/store structures
     bool v8_VLD_multiple(bool D, Reg n, size_t Vd, Imm<4> type, size_t sz, size_t align, Reg m);
 };