frontend/ir_emitter: Add half-precision opcode variant for FPVectorRSqrtEstimate
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4 changed files with 8 additions and 0 deletions
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@ -1241,6 +1241,10 @@ static void EmitRSqrtEstimate(BlockOfCode& code, EmitContext& ctx, IR::Inst* ins
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});
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}
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void EmitX64::EmitFPVectorRSqrtEstimate16(EmitContext& ctx, IR::Inst* inst) {
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EmitRSqrtEstimate<u16>(code, ctx, inst);
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}
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void EmitX64::EmitFPVectorRSqrtEstimate32(EmitContext& ctx, IR::Inst* inst) {
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EmitRSqrtEstimate<u32>(code, ctx, inst);
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}
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@ -2302,6 +2302,8 @@ U128 IREmitter::FPVectorRoundInt(size_t esize, const U128& operand, FP::Rounding
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U128 IREmitter::FPVectorRSqrtEstimate(size_t esize, const U128& a) {
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switch (esize) {
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case 16:
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return Inst<U128>(Opcode::FPVectorRSqrtEstimate16, a);
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case 32:
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return Inst<U128>(Opcode::FPVectorRSqrtEstimate32, a);
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case 64:
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@ -343,6 +343,7 @@ bool Inst::ReadsFromAndWritesToFPSRCumulativeExceptionBits() const {
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case Opcode::FPVectorRoundInt16:
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case Opcode::FPVectorRoundInt32:
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case Opcode::FPVectorRoundInt64:
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case Opcode::FPVectorRSqrtEstimate16:
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case Opcode::FPVectorRSqrtEstimate32:
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case Opcode::FPVectorRSqrtEstimate64:
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case Opcode::FPVectorRSqrtStepFused32:
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@ -578,6 +578,7 @@ OPCODE(FPVectorRecipStepFused64, U128, U128
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OPCODE(FPVectorRoundInt16, U128, U128, U8, U1 )
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OPCODE(FPVectorRoundInt32, U128, U128, U8, U1 )
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OPCODE(FPVectorRoundInt64, U128, U128, U8, U1 )
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OPCODE(FPVectorRSqrtEstimate16, U128, U128 )
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OPCODE(FPVectorRSqrtEstimate32, U128, U128 )
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OPCODE(FPVectorRSqrtEstimate64, U128, U128 )
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OPCODE(FPVectorRSqrtStepFused32, U128, U128, U128 )
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