From 01a9a12c84297bd828e0b84864778e4f2b4b7c24 Mon Sep 17 00:00:00 2001 From: Merry Date: Sat, 26 Nov 2022 16:49:42 +0000 Subject: [PATCH] test_generator: Filter out for unimplemented IR instructions --- tests/test_generator.cpp | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/tests/test_generator.cpp b/tests/test_generator.cpp index 612246af..d54d719c 100644 --- a/tests/test_generator.cpp +++ b/tests/test_generator.cpp @@ -64,7 +64,48 @@ bool ShouldTestInst(IR::Block& block) { case IR::Opcode::A64CallSupervisor: case IR::Opcode::A64DataCacheOperationRaised: case IR::Opcode::A64GetCNTPCT: + // Unimplemented + case IR::Opcode::SignedSaturatedAdd8: + case IR::Opcode::SignedSaturatedAdd16: + case IR::Opcode::SignedSaturatedAdd32: + case IR::Opcode::SignedSaturatedAdd64: + case IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh16: + case IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh32: + case IR::Opcode::SignedSaturatedSub8: + case IR::Opcode::SignedSaturatedSub16: + case IR::Opcode::SignedSaturatedSub32: + case IR::Opcode::SignedSaturatedSub64: + case IR::Opcode::UnsignedSaturatedAdd8: + case IR::Opcode::UnsignedSaturatedAdd16: + case IR::Opcode::UnsignedSaturatedAdd32: + case IR::Opcode::UnsignedSaturatedAdd64: + case IR::Opcode::UnsignedSaturatedSub8: + case IR::Opcode::UnsignedSaturatedSub16: + case IR::Opcode::UnsignedSaturatedSub32: + case IR::Opcode::UnsignedSaturatedSub64: + case IR::Opcode::VectorMaxS64: + case IR::Opcode::VectorMaxU64: + case IR::Opcode::VectorMinS64: + case IR::Opcode::VectorMinU64: + case IR::Opcode::VectorMultiply64: + case IR::Opcode::SM4AccessSubstitutionBox: + // Half-prec conversions + case IR::Opcode::FPHalfToFixedS16: + case IR::Opcode::FPHalfToFixedS32: + case IR::Opcode::FPHalfToFixedS64: + case IR::Opcode::FPHalfToFixedU16: + case IR::Opcode::FPHalfToFixedU32: + case IR::Opcode::FPHalfToFixedU64: // Half-precision + case IR::Opcode::FPAbs16: + case IR::Opcode::FPMulAdd16: + case IR::Opcode::FPNeg16: + case IR::Opcode::FPRecipEstimate16: + case IR::Opcode::FPRecipExponent16: + case IR::Opcode::FPRecipStepFused16: + case IR::Opcode::FPRoundInt16: + case IR::Opcode::FPRSqrtEstimate16: + case IR::Opcode::FPRSqrtStepFused16: case IR::Opcode::FPVectorAbs16: case IR::Opcode::FPVectorEqual16: case IR::Opcode::FPVectorMulAdd16: