2016-07-01 15:01:06 +02:00
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/* This file is part of the dynarmic project.
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* Copyright (c) 2016 MerryMage
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* This software may be used and distributed according to the terms of the GNU
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* General Public License version 2 or any later version.
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*/
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#include <algorithm>
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#include <map>
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#include "backend_x64/reg_alloc.h"
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#include "common/assert.h"
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#include "common/x64/emitter.h"
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namespace Dynarmic {
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namespace BackendX64 {
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2016-07-23 00:55:00 +02:00
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static Gen::X64Reg HostLocToX64(HostLoc loc) {
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DEBUG_ASSERT(HostLocIsRegister(loc));
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// HostLoc is ordered such that the numbers line up.
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return static_cast<Gen::X64Reg>(loc);
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}
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2016-07-01 15:01:06 +02:00
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static Gen::OpArg SpillToOpArg(HostLoc loc) {
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2016-07-23 00:55:00 +02:00
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DEBUG_ASSERT(HostLocIsSpill(loc));
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2016-07-01 15:01:06 +02:00
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size_t i = static_cast<size_t>(loc) - static_cast<size_t>(HostLoc::FirstSpill);
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2016-07-18 11:28:17 +02:00
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return Gen::MDisp(Gen::R15, static_cast<int>(offsetof(JitState, Spill) + i * sizeof(u32)));
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2016-07-01 15:01:06 +02:00
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}
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2016-07-23 00:55:00 +02:00
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Gen::X64Reg RegAlloc::DefRegister(IR::Inst* def_inst, std::initializer_list<HostLoc> desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(ValueLocations(def_inst).empty(), "def_inst has already been defined");
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2016-07-01 15:01:06 +02:00
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HostLoc location = SelectARegister(desired_locations);
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if (IsRegisterOccupied(location)) {
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SpillRegister(location);
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}
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// Update state
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2016-07-23 00:55:00 +02:00
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hostloc_state[static_cast<size_t>(location)] = HostLocState::Def;
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hostloc_to_inst[static_cast<size_t>(location)] = def_inst;
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return HostLocToX64(location);
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}
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Gen::X64Reg RegAlloc::UseDefRegister(IR::Value use_value, IR::Inst* def_inst, std::initializer_list<HostLoc> desired_locations) {
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if (!use_value.IsImmediate()) {
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return UseDefRegister(use_value.GetInst(), def_inst, desired_locations);
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}
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2016-07-01 15:01:06 +02:00
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2016-07-23 00:55:00 +02:00
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return LoadImmediateIntoRegister(use_value, DefRegister(def_inst, desired_locations));
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2016-07-01 15:01:06 +02:00
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}
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2016-07-23 00:55:00 +02:00
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Gen::X64Reg RegAlloc::UseDefRegister(IR::Inst* use_inst, IR::Inst* def_inst, std::initializer_list<HostLoc> desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(ValueLocations(def_inst).empty(), "def_inst has already been defined");
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DEBUG_ASSERT_MSG(!ValueLocations(use_inst).empty(), "use_inst has not been defined");
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2016-07-01 15:01:06 +02:00
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2016-07-23 00:55:00 +02:00
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// TODO: Optimize the case when this is the last use_inst use.
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Gen::X64Reg use_reg = UseRegister(use_inst);
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Gen::X64Reg def_reg = DefRegister(def_inst, desired_locations);
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2016-07-01 15:01:06 +02:00
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code->MOV(32, Gen::R(def_reg), Gen::R(use_reg));
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return def_reg;
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}
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2016-07-23 00:55:00 +02:00
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Gen::X64Reg RegAlloc::UseRegister(IR::Value use_value, std::initializer_list<HostLoc> desired_locations) {
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if (!use_value.IsImmediate()) {
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return UseRegister(use_value.GetInst(), desired_locations);
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}
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return LoadImmediateIntoRegister(use_value, ScratchRegister(desired_locations));
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}
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Gen::X64Reg RegAlloc::UseRegister(IR::Inst* use_inst, std::initializer_list<HostLoc> desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(!ValueLocations(use_inst).empty(), "use_inst has not been defined");
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2016-07-01 15:01:06 +02:00
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2016-07-23 00:55:00 +02:00
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HostLoc current_location = ValueLocations(use_inst).front();
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2016-07-01 15:01:06 +02:00
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auto iter = std::find(desired_locations.begin(), desired_locations.end(), current_location);
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if (iter != desired_locations.end()) {
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2016-07-23 00:55:00 +02:00
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ASSERT(hostloc_state[static_cast<size_t>(current_location)] == HostLocState::Idle || hostloc_state[static_cast<size_t>(current_location)] == HostLocState::Use);
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2016-07-01 15:01:06 +02:00
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// Update state
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2016-07-23 00:55:00 +02:00
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hostloc_state[static_cast<size_t>(current_location)] = HostLocState::Use;
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DecrementRemainingUses(use_inst);
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2016-07-01 15:01:06 +02:00
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2016-07-23 00:55:00 +02:00
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return HostLocToX64(current_location);
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2016-07-01 15:01:06 +02:00
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}
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HostLoc new_location = SelectARegister(desired_locations);
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if (HostLocIsSpill(current_location)) {
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if (IsRegisterOccupied(new_location)) {
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SpillRegister(new_location);
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}
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2016-07-23 00:55:00 +02:00
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code->MOV(32, Gen::R(HostLocToX64(new_location)), SpillToOpArg(current_location));
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2016-07-01 15:01:06 +02:00
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2016-07-23 00:55:00 +02:00
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hostloc_state[static_cast<size_t>(new_location)] = HostLocState::Use;
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std::swap(hostloc_to_inst[static_cast<size_t>(new_location)], hostloc_to_inst[static_cast<size_t>(current_location)]);
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DecrementRemainingUses(use_inst);
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2016-07-01 15:01:06 +02:00
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} else if (HostLocIsRegister(current_location)) {
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2016-07-23 00:55:00 +02:00
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ASSERT(hostloc_state[static_cast<size_t>(current_location)] == HostLocState::Idle);
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2016-07-01 15:01:06 +02:00
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2016-07-23 00:55:00 +02:00
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code->XCHG(32, Gen::R(HostLocToX64(new_location)), Gen::R(HostLocToX64(current_location)));
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2016-07-01 15:01:06 +02:00
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2016-07-23 00:55:00 +02:00
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hostloc_state[static_cast<size_t>(new_location)] = HostLocState::Use;
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std::swap(hostloc_to_inst[static_cast<size_t>(new_location)], hostloc_to_inst[static_cast<size_t>(current_location)]);
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DecrementRemainingUses(use_inst);
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2016-07-01 15:01:06 +02:00
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} else {
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ASSERT_MSG(0, "Invalid current_location");
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}
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2016-07-23 00:55:00 +02:00
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return HostLocToX64(new_location);
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2016-07-01 15:01:06 +02:00
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}
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2016-07-23 00:55:00 +02:00
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Gen::X64Reg RegAlloc::UseScratchRegister(IR::Value use_value, std::initializer_list<HostLoc> desired_locations) {
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if (!use_value.IsImmediate()) {
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return UseScratchRegister(use_value.GetInst(), desired_locations);
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}
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return LoadImmediateIntoRegister(use_value, ScratchRegister(desired_locations));
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}
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Gen::X64Reg RegAlloc::UseScratchRegister(IR::Inst* use_inst, std::initializer_list<HostLoc> desired_locations) {
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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DEBUG_ASSERT_MSG(!ValueLocations(use_inst).empty(), "use_inst has not been defined");
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ASSERT_MSG(use_inst->use_count != 0, "use_inst ran out of uses. (Use-d an IR::Inst* too many times)");
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2016-07-18 16:11:16 +02:00
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2016-07-23 00:55:00 +02:00
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HostLoc current_location = ValueLocations(use_inst).front();
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2016-07-18 16:11:16 +02:00
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HostLoc new_location = SelectARegister(desired_locations);
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if (HostLocIsSpill(current_location)) {
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if (IsRegisterOccupied(new_location)) {
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SpillRegister(new_location);
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}
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2016-07-23 00:55:00 +02:00
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code->MOV(32, Gen::R(HostLocToX64(new_location)), SpillToOpArg(current_location));
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2016-07-18 16:11:16 +02:00
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2016-07-23 00:55:00 +02:00
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hostloc_state[static_cast<size_t>(new_location)] = HostLocState::Scratch;
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DecrementRemainingUses(use_inst);
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2016-07-18 16:11:16 +02:00
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} else if (HostLocIsRegister(current_location)) {
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2016-07-23 00:55:00 +02:00
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ASSERT(hostloc_state[static_cast<size_t>(current_location)] == HostLocState::Idle);
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2016-07-18 16:11:16 +02:00
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if (IsRegisterOccupied(new_location)) {
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SpillRegister(new_location);
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2016-07-21 22:48:45 +02:00
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if (current_location != new_location) {
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2016-07-23 00:55:00 +02:00
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code->MOV(32, Gen::R(HostLocToX64(new_location)), Gen::R(HostLocToX64(current_location)));
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2016-07-21 22:48:45 +02:00
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}
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} else {
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2016-07-23 00:55:00 +02:00
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code->MOV(32, Gen::R(HostLocToX64(new_location)), Gen::R(HostLocToX64(current_location)));
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2016-07-18 16:11:16 +02:00
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}
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2016-07-23 00:55:00 +02:00
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hostloc_state[static_cast<size_t>(new_location)] = HostLocState::Scratch;
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DecrementRemainingUses(use_inst);
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2016-07-18 16:11:16 +02:00
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} else {
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ASSERT_MSG(0, "Invalid current_location");
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}
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2016-07-23 00:55:00 +02:00
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return HostLocToX64(new_location);
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2016-07-18 16:11:16 +02:00
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}
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2016-07-01 15:01:06 +02:00
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Gen::X64Reg RegAlloc::ScratchRegister(std::initializer_list<HostLoc> desired_locations) {
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2016-07-23 00:55:00 +02:00
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DEBUG_ASSERT(std::all_of(desired_locations.begin(), desired_locations.end(), HostLocIsRegister));
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2016-07-01 15:01:06 +02:00
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HostLoc location = SelectARegister(desired_locations);
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if (IsRegisterOccupied(location)) {
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SpillRegister(location);
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}
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// Update state
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2016-07-23 00:55:00 +02:00
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hostloc_state[static_cast<size_t>(location)] = HostLocState::Scratch;
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return HostLocToX64(location);
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}
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Gen::X64Reg RegAlloc::LoadImmediateIntoRegister(IR::Value imm, Gen::X64Reg reg) {
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ASSERT_MSG(imm.IsImmediate(), "imm is not an immediate");
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switch (imm.GetType()) {
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case IR::Type::U1:
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code->MOV(32, R(reg), Gen::Imm32(imm.GetU1()));
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break;
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case IR::Type::U8:
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code->MOV(32, R(reg), Gen::Imm32(imm.GetU8()));
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break;
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case IR::Type::U32:
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code->MOV(32, R(reg), Gen::Imm32(imm.GetU32()));
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break;
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default:
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ASSERT_MSG(false, "This should never happen.");
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}
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2016-07-01 15:01:06 +02:00
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2016-07-23 00:55:00 +02:00
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return reg;
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2016-07-01 15:01:06 +02:00
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}
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2016-07-23 00:55:00 +02:00
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void RegAlloc::HostCall(IR::Inst* result_def, IR::Value arg0_use, IR::Value arg1_use, IR::Value arg2_use, IR::Value arg3_use) {
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2016-07-11 16:28:10 +02:00
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constexpr HostLoc AbiReturn = HostLoc::RAX;
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#ifdef _WIN32
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constexpr std::array<HostLoc, 4> AbiArgs = { HostLoc::RCX, HostLoc::RDX, HostLoc::R8, HostLoc::R9 };
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/// Caller-saved registers other than AbiReturn or AbiArgs
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constexpr std::array<HostLoc, 2> OtherCallerSave = { HostLoc::R10, HostLoc::R11 };
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#else
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constexpr std::array<HostLoc, 4> AbiArgs = { HostLoc::RDI, HostLoc::RSI, HostLoc::RDX, HostLoc::RCX };
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/// Caller-saved registers other than AbiReturn or AbiArgs
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constexpr std::array<HostLoc, 4> OtherCallerSave = { HostLoc::R8, HostLoc::R9, HostLoc::R10, HostLoc::R11 };
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#endif
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2016-07-23 00:55:00 +02:00
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const std::array<IR::Value*, 4> args = {&arg0_use, &arg1_use, &arg2_use, &arg3_use};
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2016-07-11 16:28:10 +02:00
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// TODO: This works but almost certainly leads to suboptimal generated code.
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for (HostLoc caller_save : OtherCallerSave) {
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ScratchRegister({caller_save});
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}
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if (result_def) {
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DefRegister(result_def, {AbiReturn});
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} else {
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ScratchRegister({AbiReturn});
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}
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for (size_t i = 0; i < AbiArgs.size(); i++) {
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2016-07-23 00:55:00 +02:00
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if (!args[i]->IsEmpty()) {
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UseScratchRegister(*args[i], {AbiArgs[i]});
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2016-07-11 16:28:10 +02:00
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} else {
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ScratchRegister({AbiArgs[i]});
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}
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}
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2016-07-21 22:48:45 +02:00
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ScratchRegister({HostLoc::RSP});
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code->MOV(64, Gen::R(Gen::RSP), Gen::MDisp(Gen::R15, offsetof(JitState, save_host_RSP)));
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2016-07-11 16:28:10 +02:00
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}
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2016-07-01 15:01:06 +02:00
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HostLoc RegAlloc::SelectARegister(std::initializer_list<HostLoc> desired_locations) const {
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std::vector<HostLoc> candidates = desired_locations;
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// Find all locations that have not been allocated..
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auto allocated_locs = std::partition(candidates.begin(), candidates.end(), [this](auto loc){
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return !this->IsRegisterAllocated(loc);
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});
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candidates.erase(allocated_locs, candidates.end());
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ASSERT_MSG(!candidates.empty(), "All candidate registers have already been allocated");
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// Selects the best location out of the available locations.
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// TODO: Actually do LRU or something. Currently we just try to pick something without a value if possible.
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std::partition(candidates.begin(), candidates.end(), [this](auto loc){
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return !this->IsRegisterOccupied(loc);
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});
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return candidates.front();
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}
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2016-07-23 00:55:00 +02:00
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std::vector<HostLoc> RegAlloc::ValueLocations(IR::Inst* value) const {
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2016-07-01 15:01:06 +02:00
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std::vector<HostLoc> locations;
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2016-07-23 00:55:00 +02:00
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for (size_t i = 0; i < HostLocCount; i++)
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if (hostloc_to_inst[i] == value)
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locations.emplace_back(static_cast<HostLoc>(i));
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2016-07-01 15:01:06 +02:00
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return locations;
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}
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bool RegAlloc::IsRegisterOccupied(HostLoc loc) const {
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2016-07-23 00:55:00 +02:00
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return hostloc_to_inst.at(static_cast<size_t>(loc)) != nullptr;
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2016-07-01 15:01:06 +02:00
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}
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bool RegAlloc::IsRegisterAllocated(HostLoc loc) const {
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2016-07-23 00:55:00 +02:00
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return hostloc_state.at(static_cast<size_t>(loc)) != HostLocState::Idle;
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2016-07-01 15:01:06 +02:00
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}
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void RegAlloc::SpillRegister(HostLoc loc) {
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ASSERT_MSG(HostLocIsRegister(loc), "Only registers can be spilled");
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2016-07-23 00:55:00 +02:00
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ASSERT_MSG(hostloc_state[static_cast<size_t>(loc)] == HostLocState::Idle, "Allocated registers cannot be spilled");
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2016-07-01 15:01:06 +02:00
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ASSERT_MSG(IsRegisterOccupied(loc), "There is no need to spill unoccupied registers");
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|
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ASSERT_MSG(!IsRegisterAllocated(loc), "Registers that have been allocated must not be spilt");
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|
|
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|
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HostLoc new_loc = FindFreeSpill();
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2016-07-23 00:55:00 +02:00
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|
|
code->MOV(32, SpillToOpArg(new_loc), Gen::R(HostLocToX64(loc)));
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2016-07-01 15:01:06 +02:00
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|
2016-07-23 00:55:00 +02:00
|
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|
hostloc_to_inst[static_cast<size_t>(new_loc)] = hostloc_to_inst[static_cast<size_t>(loc)];
|
|
|
|
hostloc_to_inst[static_cast<size_t>(loc)] = nullptr;
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2016-07-01 15:01:06 +02:00
|
|
|
}
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|
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|
|
|
|
HostLoc RegAlloc::FindFreeSpill() const {
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|
|
|
for (size_t i = 0; i < SpillCount; i++)
|
|
|
|
if (!IsRegisterOccupied(HostLocSpill(i)))
|
|
|
|
return HostLocSpill(i);
|
|
|
|
|
|
|
|
ASSERT_MSG(0, "All spill locations are full");
|
|
|
|
}
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|
|
|
|
|
|
|
void RegAlloc::EndOfAllocScope() {
|
2016-07-23 00:55:00 +02:00
|
|
|
hostloc_state.fill(HostLocState::Idle);
|
2016-07-01 15:01:06 +02:00
|
|
|
|
2016-07-23 00:55:00 +02:00
|
|
|
for (auto& iter : hostloc_to_inst)
|
|
|
|
if (iter && iter->use_count == 0)
|
|
|
|
iter = nullptr;
|
2016-07-01 15:01:06 +02:00
|
|
|
}
|
|
|
|
|
2016-07-23 00:55:00 +02:00
|
|
|
void RegAlloc::DecrementRemainingUses(IR::Inst* value) {
|
|
|
|
ASSERT_MSG(value->use_count > 0, "value doesn't have any remaining uses");
|
|
|
|
value->use_count--;
|
2016-07-11 23:43:53 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void RegAlloc::AssertNoMoreUses() {
|
2016-07-23 00:55:00 +02:00
|
|
|
ASSERT(std::all_of(hostloc_to_inst.begin(), hostloc_to_inst.end(), [](const auto& inst){ return !inst; }));
|
2016-07-11 23:43:53 +02:00
|
|
|
}
|
|
|
|
|
2016-07-04 15:37:50 +02:00
|
|
|
void RegAlloc::Reset() {
|
2016-07-23 00:55:00 +02:00
|
|
|
hostloc_to_inst.fill(nullptr);
|
|
|
|
hostloc_state.fill(HostLocState::Idle);
|
2016-07-04 15:37:50 +02:00
|
|
|
}
|
|
|
|
|
2016-07-01 15:01:06 +02:00
|
|
|
} // namespace BackendX64
|
|
|
|
} // namespace Dynarmic
|