243 lines
5.8 KiB
C++
243 lines
5.8 KiB
C++
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// SPDX-FileCopyrightText: Copyright (c) 2022 merryhime <https://mary.rs>
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// SPDX-License-Identifier: MIT
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#pragma once
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namespace oaknut {
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struct PostIndexed {};
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struct PreIndexed {};
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enum class LslSymbol {
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LSL,
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};
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enum class MslSymbol {
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MSL,
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};
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enum class Cond {
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EQ,
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NE,
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CS,
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CC,
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MI,
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PL,
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VS,
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VC,
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HI,
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LS,
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GE,
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LT,
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GT,
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LE,
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AL,
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NV,
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HS = CS,
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LO = CC,
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};
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constexpr Cond invert(Cond c)
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{
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return static_cast<Cond>(static_cast<unsigned>(c) ^ 1);
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}
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enum class AddSubExt {
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UXTB,
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UXTH,
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UXTW,
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UXTX,
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SXTB,
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SXTH,
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SXTW,
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SXTX,
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LSL, // UXTW (32-bit) or UXTX (64-bit)
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};
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enum class IndexExt {
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UXTW = 0b010,
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LSL = 0b011,
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SXTW = 0b110,
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SXTX = 0b111,
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};
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enum class AddSubShift {
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LSL,
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LSR,
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ASR,
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};
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enum class LogShift {
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LSL,
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LSR,
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ASR,
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ROR,
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};
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enum class PstateField {
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UAO = 0b000'011, // ARMv8.2-UAO
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PAN = 0b000'100, // ARMv8.1-PAN
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SPSel = 0b000'101,
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DIT = 0b011'010, // ARMv8.4-DIT
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DAIFSet = 0b011'110,
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DAIFClr = 0b011'111,
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};
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enum class SystemReg {
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};
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enum class AtOp {
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S1E1R = 0b000'0'000,
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S1E1W = 0b000'0'001,
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S1E0R = 0b000'0'010,
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S1E0W = 0b000'0'011,
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S1E1RP = 0b000'1'000, // ARMv8.2-ATS1E1
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S1E1WP = 0b000'1'001, // ARMv8.2-ATS1E1
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S1E2R = 0b100'0'000,
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S1E2W = 0b100'0'001,
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S12E1R = 0b100'0'100,
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S12E1W = 0b100'0'101,
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S12E0R = 0b100'0'110,
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S12E0W = 0b100'0'111,
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S1E3R = 0b110'0'000,
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S1E3W = 0b110'0'001,
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};
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enum class BarrierOp {
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SY = 0b1111,
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ST = 0b1110,
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LD = 0b1101,
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ISH = 0b1011,
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ISHST = 0b1010,
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ISHLD = 0b1001,
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NSH = 0b0111,
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NSHST = 0b0110,
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NSHLD = 0b0101,
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OSH = 0b0011,
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OSHST = 0b0010,
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OSHLD = 0b0001,
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};
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enum class DcOp {
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IVAC = 0b000'0110'001,
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ISW = 0b000'0110'010,
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CSW = 0b000'1010'010,
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CISW = 0b000'1110'010,
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ZVA = 0b011'0100'001,
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CVAC = 0b011'1010'001,
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CVAU = 0b011'1011'001,
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CVAP = 0b011'1100'001, // ARMv8.2-DCPoP
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CIVAC = 0b011'1110'001,
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};
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enum class IcOp {
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IALLUIS = 0b000'0001'000,
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IALLU = 0b000'0101'000,
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IVAU = 0b011'0101'001,
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};
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enum class PrfOp {
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PLDL1KEEP = 0b00'00'0,
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PLDL1STRM = 0b00'00'1,
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PLDL2KEEP = 0b00'01'0,
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PLDL2STRM = 0b00'01'1,
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PLDL3KEEP = 0b00'10'0,
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PLDL3STRM = 0b00'10'1,
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PLIL1KEEP = 0b01'00'0,
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PLIL1STRM = 0b01'00'1,
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PLIL2KEEP = 0b01'01'0,
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PLIL2STRM = 0b01'01'1,
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PLIL3KEEP = 0b01'10'0,
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PLIL3STRM = 0b01'10'1,
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PSTL1KEEP = 0b10'00'0,
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PSTL1STRM = 0b10'00'1,
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PSTL2KEEP = 0b10'01'0,
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PSTL2STRM = 0b10'01'1,
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PSTL3KEEP = 0b10'10'0,
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PSTL3STRM = 0b10'10'1,
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};
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enum class TlbiOp {
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VMALLE1OS = 0b000'0001'000, // ARMv8.4-TLBI
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VAE1OS = 0b000'0001'001, // ARMv8.4-TLBI
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ASIDE1OS = 0b000'0001'010, // ARMv8.4-TLBI
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VAAE1OS = 0b000'0001'011, // ARMv8.4-TLBI
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VALE1OS = 0b000'0001'101, // ARMv8.4-TLBI
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VAALE1OS = 0b000'0001'111, // ARMv8.4-TLBI
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RVAE1IS = 0b000'0010'001, // ARMv8.4-TLBI
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RVAAE1IS = 0b000'0010'011, // ARMv8.4-TLBI
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RVALE1IS = 0b000'0010'101, // ARMv8.4-TLBI
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RVAALE1IS = 0b000'0010'111, // ARMv8.4-TLBI
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VMALLE1IS = 0b000'0011'000,
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VAE1IS = 0b000'0011'001,
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ASIDE1IS = 0b000'0011'010,
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VAAE1IS = 0b000'0011'011,
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VALE1IS = 0b000'0011'101,
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VAALE1IS = 0b000'0011'111,
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RVAE1OS = 0b000'0101'001, // ARMv8.4-TLBI
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RVAAE1OS = 0b000'0101'011, // ARMv8.4-TLBI
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RVALE1OS = 0b000'0101'101, // ARMv8.4-TLBI
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RVAALE1OS = 0b000'0101'111, // ARMv8.4-TLBI
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RVAE1 = 0b000'0110'001, // ARMv8.4-TLBI
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RVAAE1 = 0b000'0110'011, // ARMv8.4-TLBI
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RVALE1 = 0b000'0110'101, // ARMv8.4-TLBI
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RVAALE1 = 0b000'0110'111, // ARMv8.4-TLBI
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VMALLE1 = 0b000'0111'000,
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VAE1 = 0b000'0111'001,
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ASIDE1 = 0b000'0111'010,
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VAAE1 = 0b000'0111'011,
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VALE1 = 0b000'0111'101,
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VAALE1 = 0b000'0111'111,
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IPAS2E1IS = 0b100'0000'001,
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RIPAS2E1IS = 0b100'0000'010, // ARMv8.4-TLBI
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IPAS2LE1IS = 0b100'0000'101,
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RIPAS2LE1IS = 0b100'0000'110, // ARMv8.4-TLBI
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ALLE2OS = 0b100'0001'000, // ARMv8.4-TLBI
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VAE2OS = 0b100'0001'001, // ARMv8.4-TLBI
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ALLE1OS = 0b100'0001'100, // ARMv8.4-TLBI
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VALE2OS = 0b100'0001'101, // ARMv8.4-TLBI
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VMALLS12E1OS = 0b100'0001'110, // ARMv8.4-TLBI
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RVAE2IS = 0b100'0010'001, // ARMv8.4-TLBI
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RVALE2IS = 0b100'0010'101, // ARMv8.4-TLBI
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ALLE2IS = 0b100'0011'000,
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VAE2IS = 0b100'0011'001,
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ALLE1IS = 0b100'0011'100,
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VALE2IS = 0b100'0011'101,
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VMALLS12E1IS = 0b100'0011'110,
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IPAS2E1OS = 0b100'0100'000, // ARMv8.4-TLBI
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IPAS2E1 = 0b100'0100'001,
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RIPAS2E1 = 0b100'0100'010, // ARMv8.4-TLBI
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RIPAS2E1OS = 0b100'0100'011, // ARMv8.4-TLBI
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IPAS2LE1OS = 0b100'0100'100, // ARMv8.4-TLBI
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IPAS2LE1 = 0b100'0100'101,
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RIPAS2LE1 = 0b100'0100'110, // ARMv8.4-TLBI
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RIPAS2LE1OS = 0b100'0100'111, // ARMv8.4-TLBI
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RVAE2OS = 0b100'0101'001, // ARMv8.4-TLBI
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RVALE2OS = 0b100'0101'101, // ARMv8.4-TLBI
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RVAE2 = 0b100'0110'001, // ARMv8.4-TLBI
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RVALE2 = 0b100'0110'101, // ARMv8.4-TLBI
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ALLE2 = 0b100'0111'000,
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VAE2 = 0b100'0111'001,
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ALLE1 = 0b100'0111'100,
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VALE2 = 0b100'0111'101,
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VMALLS12E1 = 0b100'0111'110,
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ALLE3OS = 0b110'0001'000, // ARMv8.4-TLBI
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VAE3OS = 0b110'0001'001, // ARMv8.4-TLBI
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VALE3OS = 0b110'0001'101, // ARMv8.4-TLBI
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RVAE3IS = 0b110'0010'001, // ARMv8.4-TLBI
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RVALE3IS = 0b110'0010'101, // ARMv8.4-TLBI
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ALLE3IS = 0b110'0011'000,
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VAE3IS = 0b110'0011'001,
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VALE3IS = 0b110'0011'101,
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RVAE3OS = 0b110'0101'001, // ARMv8.4-TLBI
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RVALE3OS = 0b110'0101'101, // ARMv8.4-TLBI
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RVAE3 = 0b110'0110'001, // ARMv8.4-TLBI
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RVALE3 = 0b110'0110'101, // ARMv8.4-TLBI
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ALLE3 = 0b110'0111'000,
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VAE3 = 0b110'0111'001,
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VALE3 = 0b110'0111'101,
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};
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} // namespace oaknut
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