A C# ARM64 emulator that works translating ARM code to CIL
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jduncanator c2aaf78d4c Timing: Optimize Timestamp Aquisition (#479)
* Timing: Optimize Timestamp Aquisition

Currently, we make use of Environment.TickCount in a number of places. This has some downsides, mainly being that the TickCount is a signed 32-bit integer, and has an effective limit of ~25 days before overflowing and wrapping around. Due to the signed-ness of the value, this also caused issues with negative numbers. This resolves these issues by using a 64-bit tick count obtained from Performance Counters (via the Stopwatch class). This has a beneficial side effect of being significantly more accurate than the TickCount.

* Timing: Rename ElapsedTicks to ElapsedMilliseconds and expose TicksPerX

* Timing: Some style changes

* Timing: Align static variable initialization
2018-10-28 19:31:13 -03:00
Decoder Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449) 2018-10-13 23:35:16 -03:00
Decoder32 Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
Events Print stack trace on invalid memory accesses (#461) 2018-10-20 22:07:52 +00:00
Exceptions More flexible memory manager (#307) 2018-08-15 15:59:51 -03:00
Instruction Add SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1 and Isb instructions; add 6 Tests (closed box). (#483) 2018-10-28 19:27:50 -03:00
Instruction32 Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
Memory Print stack trace on invalid memory accesses (#461) 2018-10-20 22:07:52 +00:00
State Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) 2018-10-23 11:12:45 -03:00
Translation Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480) 2018-10-25 19:10:41 -03:00
ABitUtils.cs Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407) 2018-09-08 14:24:29 -03:00
AOpCodeTable.cs Add SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1 and Isb instructions; add 6 Tests (closed box). (#483) 2018-10-28 19:27:50 -03:00
AOptimizations.cs Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437) 2018-10-05 22:45:59 -03:00
AThread.cs Fix performance regression caused by the new scheduler changes (#422) 2018-09-19 12:16:20 -03:00
ATranslatedSub.cs Remove cold methods from the CPU cache (#224) 2018-09-19 17:07:56 -03:00
ATranslatedSubType.cs Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
ATranslator.cs Remove cold methods from the CPU cache (#224) 2018-09-19 17:07:56 -03:00
ATranslatorCache.cs Timing: Optimize Timestamp Aquisition (#479) 2018-10-28 19:31:13 -03:00
ChocolArm64.csproj Add linux-x64 to RID property to make tests works on linux (#205) 2018-06-30 12:43:04 -03:00