0cda6b3cdf
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
12 lines
No EOL
192 B
C#
12 lines
No EOL
192 B
C#
namespace ChocolArm64.Decoders
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{
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interface IOpCode32Mem : IOpCode32
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{
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int Rt { get; }
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int Rn { get; }
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bool WBack { get; }
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bool IsLoad { get; }
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}
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} |