LDj3SNuD a250878bfe Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709) ... * Update CpuTestSimdShImm.cs * Update OpCodeTable.cs * Update CpuTestSimdReg.cs * Add Ins_Gp & Ins_V Tests. Improve Smov_S & Umov_S Tests. * Add Bic_Vi & Orr_Vi Tests. * OpTable Fixes for Bic_Vi & Orr_Vi Insts. * Add Saddlv_V & Uaddlv_V Tests. * Nit. * Add Smull_V & Umull_V Tests. Improve Simd Permute Tests. * Nit. * Add Fcsel_S Test. * Add Fnmadd_S, Fnmsub_S & Fnmul_S Tests. * Fmov_V -> Fmov_Vi * OpTable Fixes for Fmov_Si & Fmov_Vi Insts. * Add Fmov_Vi Test. * Add Fmov_S Test. * Add Fmov_Si Test. Add new test category SimdFmov. * Nit. * OpTable Fixes for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. * Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. Small simpl. for Smov_S Inst. Remove unnecessary method EmitIntZeroUpperIfNeeded. * Add Fmov_Ftoi/1 & Fmov_Itof/1 Tests.		2019-06-29 20:02:48 -03:00
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CryptoHelper.cs	Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566)	2019-01-29 10:54:39 -03:00
Inst.cs	Add ARM32 support on the translator (#561)	2019-01-24 23:59:53 -02:00
InstEmit32Helper.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitAlu.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitAlu32.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitAluHelper.cs	Implement some ARM32 memory instructions and CMP (#565)	2019-01-29 13:06:11 -03:00
InstEmitBfm.cs	Optmize BFM instruction (#607)	2019-02-26 20:16:50 +11:00
InstEmitCcmp.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitCsel.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitException.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitFlow.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitFlow32.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitFlowHelper.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitHash.cs	Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)	2018-10-30 22:43:02 -03:00
InstEmitMemory.cs	Optimize address translation and write tracking on the MMU (#571)	2019-02-24 18:24:35 +11:00
InstEmitMemory32.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitMemoryEx.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitMemoryHelper.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitMove.cs	Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)	2018-10-30 22:43:02 -03:00
InstEmitMul.cs	Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)	2018-10-30 22:43:02 -03:00
InstEmitSimdArithmetic.cs	Add Smaxv_V, Sminv_V, Umaxv_V, Uminv_V Inst.; add Tests. (#691)	2019-05-29 21:29:24 -03:00
InstEmitSimdCmp.cs	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
InstEmitSimdCrypto.cs	Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)	2018-10-30 22:43:02 -03:00
InstEmitSimdCvt.cs	Add FCVT <Hd>, <Sn> and FCVT <Sd>, <Hn> Inst.; add Tests. (#692)	2019-05-30 19:51:39 -03:00
InstEmitSimdHash.cs	Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)	2018-10-30 22:43:02 -03:00
InstEmitSimdHelper.cs	Add Smaxv_V, Sminv_V, Umaxv_V, Uminv_V Inst.; add Tests. (#691)	2019-05-29 21:29:24 -03:00
InstEmitSimdLogical.cs	Add Cmeq_V, Cmge_V, Cmgt_V, Cmle_V & Cmlt_V (Z & ~Z) Sse opt.. (#646)	2019-03-25 10:23:27 +11:00
InstEmitSimdMemory.cs	Optimize address translation and write tracking on the MMU (#571)	2019-02-24 18:24:35 +11:00
InstEmitSimdMove.cs	Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709)	2019-06-29 20:02:48 -03:00
InstEmitSimdShift.cs	Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614)	2019-03-13 19:23:52 +11:00
InstEmitSystem.cs	Optimize address translation and write tracking on the MMU (#571)	2019-02-24 18:24:35 +11:00
InstEmitter.cs	Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)	2018-10-30 22:43:02 -03:00
SoftFallback.cs	Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566)	2019-01-29 10:54:39 -03:00
SoftFloat.cs	Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566)	2019-01-29 10:54:39 -03:00
VectorHelper.cs	Sse optimized the Scalar & Vector fp-to-fp conversion instructions (MNPZ & IX); added the related Tests (AMNPZ & IX). Small refactoring of existing instructions. (#676)	2019-04-26 08:58:29 +10:00