ryujinx-backup/ChocolArm64
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A C# ARM64 emulator that works translating ARM code to CIL
133 commits 1 branch 0 tags 910 KiB
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LDj3SNuD 1be39f720f Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390) 
* Update AOpCodeTable.cs

* Update AInstEmitSimdCvt.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Add QCFlagBit.

* Add QCFlagBit.
2018-09-01 11:52:51 -03:00
Decoder Added support for more shader instructions and texture formats, fix swapped channels in RGB565 and RGBA5551? texture formats, allow zero values on blending registers, initial work to build CFG on the shader decoder, update the BRA instruction to work with it (WIP) 2018-05-29 20:37:10 -03:00
Decoder32 Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
Events Implement SvcGetThreadContext3 2018-06-26 01:10:15 -03:00
Exceptions More flexible memory manager (#307) 2018-08-15 15:59:51 -03:00
Instruction Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390) 2018-09-01 11:52:51 -03:00
Instruction32 Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
Memory Code style fixes and nits on the HLE project (#355) 2018-08-16 20:47:36 -03:00
State Code style fixes and nits on the HLE project (#355) 2018-08-16 20:47:36 -03:00
Translation Code style fixes and nits on the HLE project (#355) 2018-08-16 20:47:36 -03:00
ABitUtils.cs Split main project into core,graphics and chocolarm4 subproject (#29) 2018-02-20 17:09:23 -03:00
AOpCodeTable.cs Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390) 2018-09-01 11:52:51 -03:00
AOptimizations.cs More flexible memory manager (#307) 2018-08-15 15:59:51 -03:00
AThread.cs Code style fixes and nits on the HLE project (#355) 2018-08-16 20:47:36 -03:00
ATranslatedSub.cs [CPU] Speed up translation a little bit 2018-04-11 14:44:03 -03:00
ATranslatedSubType.cs Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
ATranslator.cs Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
ChocolArm64.csproj Add linux-x64 to RID property to make tests works on linux (#205) 2018-06-30 12:43:04 -03:00