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Add Sadalp_V, Saddlp_V, Uadalp_V, Uaddlp_V instructions; add 8 Tests. (#340)

Browse source 
* Update Instructions.cs

* Update CpuTestSimd.cs

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs
This commit is contained in:
LDj3SNuD 2018-08-13 23:10:02 +02:00 committed by gdkchan
parent ce286149c6
commit fc015322bc
2 changed files with 59 additions and 0 deletions
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4
AOpCodeTable.cs
View file

@ -360,6 +360,8 @@ namespace ChocolArm64
SetA64("0x001110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Sabal_V, typeof(AOpCodeSimdReg)); SetA64("0x001110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Sabal_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Sabd_V, typeof(AOpCodeSimdReg)); SetA64("0x001110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Sabd_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Sabdl_V, typeof(AOpCodeSimdReg)); SetA64("0x001110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Sabdl_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<100000011010xxxxxxxxxx", AInstEmit.Sadalp_V, typeof(AOpCodeSimd));
SetA64("0x001110<<100000001010xxxxxxxxxx", AInstEmit.Saddlp_V, typeof(AOpCodeSimd));
SetA64("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg)); SetA64("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg));
SetA64("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt)); SetA64("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt));
SetA64("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd)); SetA64("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd));
@ -429,7 +431,9 @@ namespace ChocolArm64
SetA64("0x101110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Uabal_V, typeof(AOpCodeSimdReg)); SetA64("0x101110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Uabal_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Uabd_V, typeof(AOpCodeSimdReg)); SetA64("0x101110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Uabd_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Uabdl_V, typeof(AOpCodeSimdReg)); SetA64("0x101110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Uabdl_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<100000011010xxxxxxxxxx", AInstEmit.Uadalp_V, typeof(AOpCodeSimd));
SetA64("0x101110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Uaddl_V, typeof(AOpCodeSimdReg)); SetA64("0x101110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Uaddl_V, typeof(AOpCodeSimdReg));
SetA64("0x101110<<100000001010xxxxxxxxxx", AInstEmit.Uaddlp_V, typeof(AOpCodeSimd));
SetA64("001011100x110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd)); SetA64("001011100x110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd));
SetA64("01101110<<110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd)); SetA64("01101110<<110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd));
SetA64("0x101110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Uaddw_V, typeof(AOpCodeSimdReg)); SetA64("0x101110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Uaddw_V, typeof(AOpCodeSimdReg));

55
Instruction/AInstEmitSimdArithmetic.cs
View file

@ -158,6 +158,41 @@ namespace ChocolArm64.Instruction
Context.MarkLabel(LblTrue); Context.MarkLabel(LblTrue);
} }
private static void EmitAddLongPairwise(AILEmitterCtx Context, bool Signed, bool Accumulate)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
int Words = Op.GetBitsCount() >> 4;
int Pairs = Words >> Op.Size;
for (int Index = 0; Index < Pairs; Index++)
{
int Idx = Index << 1;
EmitVectorExtract(Context, Op.Rn, Idx, Op.Size, Signed);
EmitVectorExtract(Context, Op.Rn, Idx + 1, Op.Size, Signed);
Context.Emit(OpCodes.Add);
if (Accumulate)
{
EmitVectorExtract(Context, Op.Rd, Index, Op.Size + 1, Signed);
Context.Emit(OpCodes.Add);
}
EmitVectorInsertTmp(Context, Index, Op.Size + 1);
}
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
private static void EmitDoublingMultiplyHighHalf(AILEmitterCtx Context, bool Round) private static void EmitDoublingMultiplyHighHalf(AILEmitterCtx Context, bool Round)
{ {
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
@ -992,6 +1027,16 @@ namespace ChocolArm64.Instruction
}); });
} }
public static void Sadalp_V(AILEmitterCtx Context)
{
EmitAddLongPairwise(Context, Signed: true, Accumulate: true);
}
public static void Saddlp_V(AILEmitterCtx Context)
{
EmitAddLongPairwise(Context, Signed: true, Accumulate: false);
}
public static void Saddw_V(AILEmitterCtx Context) public static void Saddw_V(AILEmitterCtx Context)
{ {
EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add)); EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
@ -1213,11 +1258,21 @@ namespace ChocolArm64.Instruction
}); });
} }
public static void Uadalp_V(AILEmitterCtx Context)
{
EmitAddLongPairwise(Context, Signed: false, Accumulate: true);
}
public static void Uaddl_V(AILEmitterCtx Context) public static void Uaddl_V(AILEmitterCtx Context)
{ {
EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Add)); EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
} }
public static void Uaddlp_V(AILEmitterCtx Context)
{
EmitAddLongPairwise(Context, Signed: false, Accumulate: false);
}
public static void Uaddlv_V(AILEmitterCtx Context) public static void Uaddlv_V(AILEmitterCtx Context)
{ {
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;