Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380)

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdCrypto.cs

AOpCodeTable.cs

@@ -374,10 +374,12 @@ namespace ChocolArm64
             SetA64("01011110000xxxxx010100xxxxxxxxxx", AInstEmit.Sha256h2_V,    typeof(AOpCodeSimdReg));
             SetA64("0101111000101000001010xxxxxxxxxx", AInstEmit.Sha256su0_V,   typeof(AOpCodeSimd));
             SetA64("01011110000xxxxx011000xxxxxxxxxx", AInstEmit.Sha256su1_V,   typeof(AOpCodeSimdReg));
+            SetA64("0x001110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Shadd_V,       typeof(AOpCodeSimdReg));
             SetA64("010111110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_S,         typeof(AOpCodeSimdShImm));
             SetA64("0x0011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V,         typeof(AOpCodeSimdShImm));
             SetA64("0x101110<<100001001110xxxxxxxxxx", AInstEmit.Shll_V,        typeof(AOpCodeSimd));
             SetA64("0x00111100>>>xxx100001xxxxxxxxxx", AInstEmit.Shrn_V,        typeof(AOpCodeSimdShImm));
+            SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Shsub_V,       typeof(AOpCodeSimdReg));
             SetA64("0x1011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Sli_V,         typeof(AOpCodeSimdShImm));
             SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Smax_V,        typeof(AOpCodeSimdReg));
             SetA64("0x001110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Smaxp_V,       typeof(AOpCodeSimdReg));
@@ -407,6 +409,7 @@ namespace ChocolArm64
             SetA64("0x001110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_V,       typeof(AOpCodeSimd));
             SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S,      typeof(AOpCodeSimd));
             SetA64("0x101110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_V,      typeof(AOpCodeSimd));
+            SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Srhadd_V,      typeof(AOpCodeSimdReg));
             SetA64("0x00111100>>>xxx001001xxxxxxxxxx", AInstEmit.Srshr_V,       typeof(AOpCodeSimdShImm));
             SetA64("0100111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_V,       typeof(AOpCodeSimdShImm));
             SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V,        typeof(AOpCodeSimdReg));
@@ -449,6 +452,7 @@ namespace ChocolArm64
             SetA64("011111100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_S,       typeof(AOpCodeSimd));
             SetA64("0x1011100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_V,       typeof(AOpCodeSimd));
             SetA64("0x101110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Uhadd_V,       typeof(AOpCodeSimdReg));
+            SetA64("0x101110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Uhsub_V,       typeof(AOpCodeSimdReg));
             SetA64("0x101110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Umax_V,        typeof(AOpCodeSimdReg));
             SetA64("0x101110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Umaxp_V,       typeof(AOpCodeSimdReg));
             SetA64("0x101110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Umin_V,        typeof(AOpCodeSimdReg));
@@ -461,6 +465,7 @@ namespace ChocolArm64
             SetA64("0>101110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Uqsub_V,       typeof(AOpCodeSimdReg));
             SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S,       typeof(AOpCodeSimd));
             SetA64("0x101110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_V,       typeof(AOpCodeSimd));
+            SetA64("0x101110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Urhadd_V,      typeof(AOpCodeSimdReg));
             SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V,        typeof(AOpCodeSimdReg));
             SetA64("0x10111100>>>xxx101001xxxxxxxxxx", AInstEmit.Ushll_V,       typeof(AOpCodeSimdShImm));
             SetA64("0111111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_S,        typeof(AOpCodeSimdShImm));

Instruction/AInstEmitSimdArithmetic.cs

@@ -1042,6 +1042,28 @@ namespace ChocolArm64.Instruction
             EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
         }
 
+        public static void Shadd_V(AILEmitterCtx Context)
+        {
+            EmitVectorBinaryOpSx(Context, () =>
+            {
+                Context.Emit(OpCodes.Add);
+
+                Context.Emit(OpCodes.Ldc_I4_1);
+                Context.Emit(OpCodes.Shr);
+            });
+        }
+
+        public static void Shsub_V(AILEmitterCtx Context)
+        {
+            EmitVectorBinaryOpSx(Context, () =>
+            {
+                Context.Emit(OpCodes.Sub);
+
+                Context.Emit(OpCodes.Ldc_I4_1);
+                Context.Emit(OpCodes.Shr);
+            });
+        }
+
         public static void Smax_V(AILEmitterCtx Context)
         {
             Type[] Types = new Type[] { typeof(long), typeof(long) };
@@ -1181,6 +1203,20 @@ namespace ChocolArm64.Instruction
             EmitVectorSaturatingNarrowOpSxZx(Context, () => { });
         }
 
+        public static void Srhadd_V(AILEmitterCtx Context)
+        {
+            EmitVectorBinaryOpSx(Context, () =>
+            {
+                Context.Emit(OpCodes.Add);
+
+                Context.Emit(OpCodes.Ldc_I4_1);
+                Context.Emit(OpCodes.Add);
+
+                Context.Emit(OpCodes.Ldc_I4_1);
+                Context.Emit(OpCodes.Shr);
+            });
+        }
+
         public static void Ssubw_V(AILEmitterCtx Context)
         {
             EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub));
@@ -1303,28 +1339,20 @@ namespace ChocolArm64.Instruction
             {
                 Context.Emit(OpCodes.Add);
 
-                Context.EmitLdc_I4(1);
+                Context.Emit(OpCodes.Ldc_I4_1);
-
                 Context.Emit(OpCodes.Shr_Un);
             });
         }
 
-        public static void Umin_V(AILEmitterCtx Context)
+        public static void Uhsub_V(AILEmitterCtx Context)
         {
-            Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
+            EmitVectorBinaryOpZx(Context, () =>
+            {
+                Context.Emit(OpCodes.Sub);
 
-            MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
+                Context.Emit(OpCodes.Ldc_I4_1);
-
+                Context.Emit(OpCodes.Shr_Un);
-            EmitVectorBinaryOpZx(Context, () => Context.EmitCall(MthdInfo));
+            });
-        }
-
-        public static void Uminp_V(AILEmitterCtx Context)
-        {
-            Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
-
-            MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
-
-            EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
         }
 
         public static void Umax_V(AILEmitterCtx Context)
@@ -1345,6 +1373,24 @@ namespace ChocolArm64.Instruction
             EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
         }
 
+        public static void Umin_V(AILEmitterCtx Context)
+        {
+            Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
+
+            MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
+
+            EmitVectorBinaryOpZx(Context, () => Context.EmitCall(MthdInfo));
+        }
+
+        public static void Uminp_V(AILEmitterCtx Context)
+        {
+            Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
+
+            MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
+
+            EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
+        }
+
         public static void Umull_V(AILEmitterCtx Context)
         {
             EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
@@ -1380,6 +1426,20 @@ namespace ChocolArm64.Instruction
             EmitVectorSaturatingNarrowOpZxZx(Context, () => { });
         }
 
+        public static void Urhadd_V(AILEmitterCtx Context)
+        {
+            EmitVectorBinaryOpZx(Context, () =>
+            {
+                Context.Emit(OpCodes.Add);
+
+                Context.Emit(OpCodes.Ldc_I4_1);
+                Context.Emit(OpCodes.Add);
+
+                Context.Emit(OpCodes.Ldc_I4_1);
+                Context.Emit(OpCodes.Shr_Un);
+            });
+        }
+
         public static void Usqadd_S(AILEmitterCtx Context)
         {
             EmitScalarSaturatingBinaryOpZx(Context, SaturatingFlags.Accumulate);