Misc. CPU optimizations (#575)
* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0 * Refactoring * Add a config entry to enable or disable the reg load/store opt. * Remove unnecessary register state stores for calls when the callee is know * Rename IoType to VarType * Enable tier 0 while fixing some perf issues related to tier 0 * Small tweak -- Compile before adding to the cache, to avoid lags * Add required config entry
This commit is contained in:
gdkchan
jduncanator
parent
f2d37d52f7
commit
8d5a48ba0a
25 changed files with 424 additions and 273 deletions
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@ -39,7 +39,6 @@ namespace ChocolArm64.Instructions
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context.EmitLdc_I(op.Position + 4);
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context.EmitStint(RegisterAlias.Lr);
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context.EmitStoreState();
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EmitCall(context, op.Imm);
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}
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@ -60,6 +59,8 @@ namespace ChocolArm64.Instructions
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{
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OpCodeBReg64 op = (OpCodeBReg64)context.CurrOp;
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context.HasIndirectJump = true;
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context.EmitStoreState();
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context.EmitLdintzr(op.Rn);
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@ -65,7 +65,6 @@ namespace ChocolArm64.Instructions
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}
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context.EmitStint(GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr));
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context.EmitStoreState();
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//If x is true, then this is a branch with link and exchange.
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//In this case we need to swap the mode between Arm <-> Thumb.
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@ -11,6 +11,8 @@ namespace ChocolArm64.Instructions
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{
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if (context.Tier == TranslationTier.Tier0)
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{
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context.EmitStoreState();
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context.TranslateAhead(imm);
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context.EmitLdc_I8(imm);
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@ -22,6 +24,10 @@ namespace ChocolArm64.Instructions
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if (!context.TryOptEmitSubroutineCall())
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{
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context.HasSlowCall = true;
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context.EmitStoreState();
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context.TranslateAhead(imm);
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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@ -32,6 +38,7 @@ namespace ChocolArm64.Instructions
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitLdc_I8(imm);
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context.EmitLdc_I4((int)CallType.Call);
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context.EmitPrivateCall(typeof(Translator), nameof(Translator.GetOrTranslateSubroutine));
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@ -58,20 +65,6 @@ namespace ChocolArm64.Instructions
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{
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if (context.Tier == TranslationTier.Tier0)
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{
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context.Emit(OpCodes.Dup);
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context.EmitSttmp();
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitFieldLoad(typeof(CpuThreadState).GetField(nameof(CpuThreadState.CurrentTranslator),
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BindingFlags.Instance |
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BindingFlags.NonPublic));
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitLdtmp();
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context.EmitPrivateCall(typeof(Translator), nameof(Translator.TranslateVirtualSubroutine));
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context.Emit(OpCodes.Ret);
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}
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else
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@ -85,8 +78,11 @@ namespace ChocolArm64.Instructions
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitLdtmp();
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context.EmitLdc_I4(isJump
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? (int)CallType.VirtualJump
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: (int)CallType.VirtualCall);
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context.EmitPrivateCall(typeof(Translator), nameof(Translator.GetOrTranslateVirtualSubroutine));
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context.EmitPrivateCall(typeof(Translator), nameof(Translator.GetOrTranslateSubroutine));
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitLdarg(TranslatedSub.MemoryArgIdx);
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@ -2,21 +2,23 @@ using System.Runtime.Intrinsics.X86;
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public static class Optimizations
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{
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internal static bool FastFP = true;
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public static bool AssumeStrictAbiCompliance { get; set; }
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private static bool _useAllSseIfAvailable = true;
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public static bool FastFP { get; set; } = true;
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private static bool _useSseIfAvailable = true;
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private static bool _useSse2IfAvailable = true;
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private static bool _useSse3IfAvailable = true;
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private static bool _useSsse3IfAvailable = true;
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private static bool _useSse41IfAvailable = true;
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private static bool _useSse42IfAvailable = true;
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private const bool UseAllSseIfAvailable = true;
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internal static bool UseSse = (_useAllSseIfAvailable && _useSseIfAvailable) && Sse.IsSupported;
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internal static bool UseSse2 = (_useAllSseIfAvailable && _useSse2IfAvailable) && Sse2.IsSupported;
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internal static bool UseSse3 = (_useAllSseIfAvailable && _useSse3IfAvailable) && Sse3.IsSupported;
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internal static bool UseSsse3 = (_useAllSseIfAvailable && _useSsse3IfAvailable) && Ssse3.IsSupported;
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internal static bool UseSse41 = (_useAllSseIfAvailable && _useSse41IfAvailable) && Sse41.IsSupported;
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internal static bool UseSse42 = (_useAllSseIfAvailable && _useSse42IfAvailable) && Sse42.IsSupported;
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public static bool UseSseIfAvailable { get; set; } = UseAllSseIfAvailable;
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public static bool UseSse2IfAvailable { get; set; } = UseAllSseIfAvailable;
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public static bool UseSse3IfAvailable { get; set; } = UseAllSseIfAvailable;
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public static bool UseSsse3IfAvailable { get; set; } = UseAllSseIfAvailable;
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public static bool UseSse41IfAvailable { get; set; } = UseAllSseIfAvailable;
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public static bool UseSse42IfAvailable { get; set; } = UseAllSseIfAvailable;
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internal static bool UseSse => UseSseIfAvailable && Sse.IsSupported;
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internal static bool UseSse2 => UseSse2IfAvailable && Sse2.IsSupported;
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internal static bool UseSse3 => UseSse3IfAvailable && Sse3.IsSupported;
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internal static bool UseSsse3 => UseSsse3IfAvailable && Ssse3.IsSupported;
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internal static bool UseSse41 => UseSse41IfAvailable && Sse41.IsSupported;
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internal static bool UseSse42 => UseSse42IfAvailable && Sse42.IsSupported;
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}
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9
Translation/CallType.cs
Normal file
9
Translation/CallType.cs
Normal file
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@ -0,0 +1,9 @@
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namespace ChocolArm64.Translation
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{
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enum CallType
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{
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Call,
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VirtualCall,
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VirtualJump
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}
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}
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@ -4,13 +4,13 @@ namespace ChocolArm64.Translation
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{
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class ILBlock : IILEmit
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{
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public long IntInputs { get; private set; }
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public long IntOutputs { get; private set; }
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public long IntAwOutputs { get; private set; }
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public long IntInputs { get; private set; }
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public long IntOutputs { get; private set; }
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private long _intAwOutputs;
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public long VecInputs { get; private set; }
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public long VecOutputs { get; private set; }
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public long VecAwOutputs { get; private set; }
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public long VecInputs { get; private set; }
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public long VecOutputs { get; private set; }
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private long _vecAwOutputs;
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public bool HasStateStore { get; private set; }
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@ -34,25 +34,25 @@ namespace ChocolArm64.Translation
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//opcodes emitted by each ARM instruction.
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//We can only consider the new outputs for doing input elimination
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//after all the CIL opcodes used by the instruction being emitted.
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IntAwOutputs = IntOutputs;
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VecAwOutputs = VecOutputs;
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_intAwOutputs = IntOutputs;
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_vecAwOutputs = VecOutputs;
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}
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else if (emitter is ILOpCodeLoad ld && ILMethodBuilder.IsRegIndex(ld.Index))
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{
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switch (ld.IoType)
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switch (ld.VarType)
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{
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case IoType.Flag: IntInputs |= ((1L << ld.Index) << 32) & ~IntAwOutputs; break;
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case IoType.Int: IntInputs |= (1L << ld.Index) & ~IntAwOutputs; break;
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case IoType.Vector: VecInputs |= (1L << ld.Index) & ~VecAwOutputs; break;
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case VarType.Flag: IntInputs |= ((1L << ld.Index) << 32) & ~_intAwOutputs; break;
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case VarType.Int: IntInputs |= (1L << ld.Index) & ~_intAwOutputs; break;
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case VarType.Vector: VecInputs |= (1L << ld.Index) & ~_vecAwOutputs; break;
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}
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}
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else if (emitter is ILOpCodeStore st && ILMethodBuilder.IsRegIndex(st.Index))
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{
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switch (st.IoType)
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switch (st.VarType)
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{
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case IoType.Flag: IntOutputs |= (1L << st.Index) << 32; break;
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case IoType.Int: IntOutputs |= 1L << st.Index; break;
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case IoType.Vector: VecOutputs |= 1L << st.Index; break;
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case VarType.Flag: IntOutputs |= (1L << st.Index) << 32; break;
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case VarType.Int: IntOutputs |= 1L << st.Index; break;
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case VarType.Vector: VecOutputs |= 1L << st.Index; break;
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}
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}
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else if (emitter is ILOpCodeStoreState)
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@ -31,6 +31,10 @@ namespace ChocolArm64.Translation
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public Aarch32Mode Mode { get; } = Aarch32Mode.User; //TODO
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public bool HasIndirectJump { get; set; }
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public bool HasSlowCall { get; set; }
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private Dictionary<Block, ILBlock> _visitedBlocks;
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private Queue<Block> _branchTargets;
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@ -91,7 +95,12 @@ namespace ChocolArm64.Translation
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ResetBlockState();
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AdvanceOpCode();
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if (AdvanceOpCode())
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{
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EmitSynchronization();
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_ilBlock.Add(new ILOpCodeLoadState(_ilBlock, isSubEntry: true));
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}
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}
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public static int GetIntTempIndex()
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@ -127,10 +136,18 @@ namespace ChocolArm64.Translation
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return;
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}
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if (_opcIndex == 0)
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int opcIndex = _opcIndex;
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if (opcIndex == 0)
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{
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MarkLabel(GetLabel(_currBlock.Position));
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}
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bool isLastOp = opcIndex == CurrBlock.OpCodes.Count - 1;
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if (isLastOp && CurrBlock.Branch != null &&
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(ulong)CurrBlock.Branch.Position <= (ulong)CurrBlock.Position)
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{
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EmitSynchronization();
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}
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@ -161,7 +178,7 @@ namespace ChocolArm64.Translation
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//of the next instruction to be executed (in the case that the condition
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//is false, and the branch was not taken, as all basic blocks should end with
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//some kind of branch).
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if (CurrOp == CurrBlock.GetLastOp() && CurrBlock.Next == null)
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if (isLastOp && CurrBlock.Next == null)
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{
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EmitStoreState();
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EmitLdc_I8(CurrOp.Position + CurrOp.OpCodeSizeInBytes);
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@ -285,32 +302,43 @@ namespace ChocolArm64.Translation
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return;
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}
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_queue.Enqueue(new TranslatorQueueItem(position, mode, TranslationTier.Tier1));
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_queue.Enqueue(position, mode, TranslationTier.Tier1, isComplete: true);
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}
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public bool TryOptEmitSubroutineCall()
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{
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//Calls should always have a next block, unless
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//we're translating a single basic block.
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if (_currBlock.Next == null)
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{
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return false;
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}
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if (CurrOp.Emitter != InstEmit.Bl)
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if (!(CurrOp is IOpCodeBImm op))
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{
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return false;
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}
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if (!_cache.TryGetSubroutine(((OpCodeBImmAl64)CurrOp).Imm, out TranslatedSub subroutine))
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if (!_cache.TryGetSubroutine(op.Imm, out TranslatedSub sub))
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{
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return false;
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}
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//It's not worth to call a Tier0 method, because
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//it contains slow code, rather than the entire function.
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if (sub.Tier == TranslationTier.Tier0)
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{
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return false;
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}
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EmitStoreState(sub);
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for (int index = 0; index < TranslatedSub.FixedArgTypes.Length; index++)
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{
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EmitLdarg(index);
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}
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EmitCall(subroutine.Method);
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EmitCall(sub.Method);
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return true;
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}
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@ -321,8 +349,8 @@ namespace ChocolArm64.Translation
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InstEmitAluHelper.EmitAluLoadOpers(this);
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Stloc(CmpOptTmp2Index, IoType.Int);
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Stloc(CmpOptTmp1Index, IoType.Int);
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Stloc(CmpOptTmp2Index, VarType.Int);
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Stloc(CmpOptTmp1Index, VarType.Int);
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}
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private Dictionary<Condition, OpCode> _branchOps = new Dictionary<Condition, OpCode>()
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@ -346,8 +374,8 @@ namespace ChocolArm64.Translation
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{
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if (_optOpLastCompare.Emitter == InstEmit.Subs)
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{
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Ldloc(CmpOptTmp1Index, IoType.Int, _optOpLastCompare.RegisterSize);
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Ldloc(CmpOptTmp2Index, IoType.Int, _optOpLastCompare.RegisterSize);
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Ldloc(CmpOptTmp1Index, VarType.Int, _optOpLastCompare.RegisterSize);
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Ldloc(CmpOptTmp2Index, VarType.Int, _optOpLastCompare.RegisterSize);
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Emit(_branchOps[cond], target);
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@ -369,7 +397,7 @@ namespace ChocolArm64.Translation
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//Such invalid values can't be encoded on the immediate encodings.
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if (_optOpLastCompare is IOpCodeAluImm64 op)
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{
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Ldloc(CmpOptTmp1Index, IoType.Int, _optOpLastCompare.RegisterSize);
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Ldloc(CmpOptTmp1Index, VarType.Int, _optOpLastCompare.RegisterSize);
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if (_optOpLastCompare.RegisterSize == RegisterSize.Int32)
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{
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@ -491,14 +519,14 @@ namespace ChocolArm64.Translation
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{
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if (amount > 0)
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{
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Stloc(RorTmpIndex, IoType.Int);
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Ldloc(RorTmpIndex, IoType.Int);
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Stloc(RorTmpIndex, VarType.Int);
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Ldloc(RorTmpIndex, VarType.Int);
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EmitLdc_I4(amount);
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Emit(OpCodes.Shr_Un);
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Ldloc(RorTmpIndex, IoType.Int);
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Ldloc(RorTmpIndex, VarType.Int);
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EmitLdc_I4(CurrOp.GetBitsCount() - amount);
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@ -546,7 +574,7 @@ namespace ChocolArm64.Translation
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public void EmitLdarg(int index)
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{
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_ilBlock.Add(new ILOpCodeLoad(index, IoType.Arg));
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_ilBlock.Add(new ILOpCodeLoad(index, VarType.Arg));
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}
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public void EmitLdintzr(int index)
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@ -588,6 +616,11 @@ namespace ChocolArm64.Translation
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_ilBlock.Add(new ILOpCodeStoreState(_ilBlock));
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}
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private void EmitStoreState(TranslatedSub callSub)
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{
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_ilBlock.Add(new ILOpCodeStoreState(_ilBlock, callSub));
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}
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public void EmitLdtmp() => EmitLdint(IntGpTmp1Index);
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public void EmitSttmp() => EmitStint(IntGpTmp1Index);
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@ -600,13 +633,13 @@ namespace ChocolArm64.Translation
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public void EmitLdvectmp2() => EmitLdvec(VecGpTmp2Index);
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public void EmitStvectmp2() => EmitStvec(VecGpTmp2Index);
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public void EmitLdint(int index) => Ldloc(index, IoType.Int);
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public void EmitStint(int index) => Stloc(index, IoType.Int);
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public void EmitLdint(int index) => Ldloc(index, VarType.Int);
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public void EmitStint(int index) => Stloc(index, VarType.Int);
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public void EmitLdvec(int index) => Ldloc(index, IoType.Vector);
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public void EmitStvec(int index) => Stloc(index, IoType.Vector);
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public void EmitLdvec(int index) => Ldloc(index, VarType.Vector);
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public void EmitStvec(int index) => Stloc(index, VarType.Vector);
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|
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public void EmitLdflg(int index) => Ldloc(index, IoType.Flag);
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public void EmitLdflg(int index) => Ldloc(index, VarType.Flag);
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public void EmitStflg(int index)
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{
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//Set this only if any of the NZCV flag bits were modified.
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@ -619,22 +652,22 @@ namespace ChocolArm64.Translation
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_optOpLastFlagSet = CurrOp;
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}
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Stloc(index, IoType.Flag);
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Stloc(index, VarType.Flag);
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}
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|
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private void Ldloc(int index, IoType ioType)
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private void Ldloc(int index, VarType varType)
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{
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_ilBlock.Add(new ILOpCodeLoad(index, ioType, CurrOp.RegisterSize));
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_ilBlock.Add(new ILOpCodeLoad(index, varType, CurrOp.RegisterSize));
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}
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private void Ldloc(int index, IoType ioType, RegisterSize registerSize)
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private void Ldloc(int index, VarType varType, RegisterSize registerSize)
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{
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_ilBlock.Add(new ILOpCodeLoad(index, ioType, registerSize));
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_ilBlock.Add(new ILOpCodeLoad(index, varType, registerSize));
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}
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|
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private void Stloc(int index, IoType ioType)
|
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private void Stloc(int index, VarType varType)
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{
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_ilBlock.Add(new ILOpCodeStore(index, ioType, CurrOp.RegisterSize));
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_ilBlock.Add(new ILOpCodeStore(index, varType, CurrOp.RegisterSize));
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}
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|
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public void EmitCallPropGet(Type objType, string propName)
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|
|
|
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@ -6,7 +6,7 @@ namespace ChocolArm64.Translation
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|||
{
|
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private bool _hasLabel;
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||||
|
||||
private Label _lbl;
|
||||
private Label _label;
|
||||
|
||||
public void Emit(ILMethodBuilder context)
|
||||
{
|
||||
|
|
@ -17,12 +17,12 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
if (!_hasLabel)
|
||||
{
|
||||
_lbl = context.Generator.DefineLabel();
|
||||
_label = context.Generator.DefineLabel();
|
||||
|
||||
_hasLabel = true;
|
||||
}
|
||||
|
||||
return _lbl;
|
||||
return _label;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -8,7 +8,10 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
class ILMethodBuilder
|
||||
{
|
||||
public LocalAlloc LocalAlloc { get; private set; }
|
||||
private const int RegsCount = 32;
|
||||
private const int RegsMask = RegsCount - 1;
|
||||
|
||||
public RegisterUsage RegUsage { get; private set; }
|
||||
|
||||
public ILGenerator Generator { get; private set; }
|
||||
|
||||
|
|
@ -18,29 +21,47 @@ namespace ChocolArm64.Translation
|
|||
|
||||
private string _subName;
|
||||
|
||||
public bool IsAarch64 { get; }
|
||||
|
||||
public bool IsSubComplete { get; }
|
||||
|
||||
private int _localsCount;
|
||||
|
||||
public ILMethodBuilder(ILBlock[] ilBlocks, string subName)
|
||||
public ILMethodBuilder(
|
||||
ILBlock[] ilBlocks,
|
||||
string subName,
|
||||
bool isAarch64,
|
||||
bool isSubComplete = false)
|
||||
{
|
||||
_ilBlocks = ilBlocks;
|
||||
_subName = subName;
|
||||
_ilBlocks = ilBlocks;
|
||||
_subName = subName;
|
||||
IsAarch64 = isAarch64;
|
||||
IsSubComplete = isSubComplete;
|
||||
}
|
||||
|
||||
public TranslatedSub GetSubroutine(TranslationTier tier)
|
||||
public TranslatedSub GetSubroutine(TranslationTier tier, bool isWorthOptimizing)
|
||||
{
|
||||
LocalAlloc = new LocalAlloc(_ilBlocks, _ilBlocks[0]);
|
||||
RegUsage = new RegisterUsage();
|
||||
|
||||
RegUsage.BuildUses(_ilBlocks[0]);
|
||||
|
||||
DynamicMethod method = new DynamicMethod(_subName, typeof(long), TranslatedSub.FixedArgTypes);
|
||||
|
||||
Generator = method.GetILGenerator();
|
||||
long intNiRegsMask = RegUsage.GetIntNotInputs(_ilBlocks[0]);
|
||||
long vecNiRegsMask = RegUsage.GetVecNotInputs(_ilBlocks[0]);
|
||||
|
||||
TranslatedSub subroutine = new TranslatedSub(method, tier);
|
||||
TranslatedSub subroutine = new TranslatedSub(
|
||||
method,
|
||||
intNiRegsMask,
|
||||
vecNiRegsMask,
|
||||
tier,
|
||||
isWorthOptimizing);
|
||||
|
||||
_locals = new Dictionary<Register, int>();
|
||||
|
||||
_localsCount = 0;
|
||||
|
||||
new ILOpCodeLoadState(_ilBlocks[0]).Emit(this);
|
||||
Generator = method.GetILGenerator();
|
||||
|
||||
foreach (ILBlock ilBlock in _ilBlocks)
|
||||
{
|
||||
|
|
@ -80,13 +101,13 @@ namespace ChocolArm64.Translation
|
|||
|
||||
public static Register GetRegFromBit(int bit, RegisterType baseType)
|
||||
{
|
||||
if (bit < 32)
|
||||
if (bit < RegsCount)
|
||||
{
|
||||
return new Register(bit, baseType);
|
||||
}
|
||||
else if (baseType == RegisterType.Int)
|
||||
{
|
||||
return new Register(bit & 0x1f, RegisterType.Flag);
|
||||
return new Register(bit & RegsMask, RegisterType.Flag);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -96,7 +117,7 @@ namespace ChocolArm64.Translation
|
|||
|
||||
public static bool IsRegIndex(int index)
|
||||
{
|
||||
return (uint)index < 32;
|
||||
return (uint)index < RegsCount;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -4,16 +4,16 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
struct ILOpCode : IILEmit
|
||||
{
|
||||
private OpCode _ilOp;
|
||||
public OpCode ILOp { get; }
|
||||
|
||||
public ILOpCode(OpCode ilOp)
|
||||
{
|
||||
_ilOp = ilOp;
|
||||
ILOp = ilOp;
|
||||
}
|
||||
|
||||
public void Emit(ILMethodBuilder context)
|
||||
{
|
||||
context.Generator.Emit(_ilOp);
|
||||
context.Generator.Emit(ILOp);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -4,18 +4,18 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
struct ILOpCodeBranch : IILEmit
|
||||
{
|
||||
private OpCode _ilOp;
|
||||
private ILLabel _label;
|
||||
public OpCode ILOp { get; }
|
||||
public ILLabel Label { get; }
|
||||
|
||||
public ILOpCodeBranch(OpCode ilOp, ILLabel label)
|
||||
{
|
||||
_ilOp = ilOp;
|
||||
_label = label;
|
||||
ILOp = ilOp;
|
||||
Label = label;
|
||||
}
|
||||
|
||||
public void Emit(ILMethodBuilder context)
|
||||
{
|
||||
context.Generator.Emit(_ilOp, _label.GetLabel(context));
|
||||
context.Generator.Emit(ILOp, Label.GetLabel(context));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -5,9 +5,9 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
struct ILOpCodeCall : IILEmit
|
||||
{
|
||||
public MethodInfo Info { get; private set; }
|
||||
public MethodInfo Info { get; }
|
||||
|
||||
public bool IsVirtual { get; private set; }
|
||||
public bool IsVirtual { get; }
|
||||
|
||||
public ILOpCodeCall(MethodInfo info, bool isVirtual)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@ namespace ChocolArm64.Translation
|
|||
|
||||
private ImmVal _value;
|
||||
|
||||
public long Value => _value.I8;
|
||||
|
||||
private enum ConstType
|
||||
{
|
||||
Int32,
|
||||
|
|
|
|||
|
|
@ -5,28 +5,28 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
struct ILOpCodeLoad : IILEmit
|
||||
{
|
||||
public int Index { get; private set; }
|
||||
public int Index { get; }
|
||||
|
||||
public IoType IoType { get; private set; }
|
||||
public VarType VarType { get; }
|
||||
|
||||
public RegisterSize RegisterSize { get; private set; }
|
||||
public RegisterSize RegisterSize { get; }
|
||||
|
||||
public ILOpCodeLoad(int index, IoType ioType, RegisterSize registerSize = 0)
|
||||
public ILOpCodeLoad(int index, VarType varType, RegisterSize registerSize = 0)
|
||||
{
|
||||
Index = index;
|
||||
IoType = ioType;
|
||||
VarType = varType;
|
||||
RegisterSize = registerSize;
|
||||
}
|
||||
|
||||
public void Emit(ILMethodBuilder context)
|
||||
{
|
||||
switch (IoType)
|
||||
switch (VarType)
|
||||
{
|
||||
case IoType.Arg: context.Generator.EmitLdarg(Index); break;
|
||||
case VarType.Arg: context.Generator.EmitLdarg(Index); break;
|
||||
|
||||
case IoType.Flag: EmitLdloc(context, Index, RegisterType.Flag); break;
|
||||
case IoType.Int: EmitLdloc(context, Index, RegisterType.Int); break;
|
||||
case IoType.Vector: EmitLdloc(context, Index, RegisterType.Vector); break;
|
||||
case VarType.Flag: EmitLdloc(context, Index, RegisterType.Flag); break;
|
||||
case VarType.Int: EmitLdloc(context, Index, RegisterType.Int); break;
|
||||
case VarType.Vector: EmitLdloc(context, Index, RegisterType.Vector); break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
struct ILOpCodeLoadField : IILEmit
|
||||
{
|
||||
public FieldInfo Info { get; private set; }
|
||||
public FieldInfo Info { get; }
|
||||
|
||||
public ILOpCodeLoadField(FieldInfo info)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -7,15 +7,24 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
private ILBlock _block;
|
||||
|
||||
public ILOpCodeLoadState(ILBlock block)
|
||||
private bool _isSubEntry;
|
||||
|
||||
public ILOpCodeLoadState(ILBlock block, bool isSubEntry = false)
|
||||
{
|
||||
_block = block;
|
||||
_block = block;
|
||||
_isSubEntry = isSubEntry;
|
||||
}
|
||||
|
||||
public void Emit(ILMethodBuilder context)
|
||||
{
|
||||
long intInputs = context.LocalAlloc.GetIntInputs(_block);
|
||||
long vecInputs = context.LocalAlloc.GetVecInputs(_block);
|
||||
long intInputs = context.RegUsage.GetIntInputs(_block);
|
||||
long vecInputs = context.RegUsage.GetVecInputs(_block);
|
||||
|
||||
if (Optimizations.AssumeStrictAbiCompliance && context.IsSubComplete)
|
||||
{
|
||||
intInputs = RegisterUsage.ClearCallerSavedIntRegs(intInputs, context.IsAarch64);
|
||||
vecInputs = RegisterUsage.ClearCallerSavedVecRegs(vecInputs, context.IsAarch64);
|
||||
}
|
||||
|
||||
LoadLocals(context, intInputs, RegisterType.Int);
|
||||
LoadLocals(context, vecInputs, RegisterType.Vector);
|
||||
|
|
|
|||
|
|
@ -2,16 +2,16 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
struct ILOpCodeLog : IILEmit
|
||||
{
|
||||
private string _text;
|
||||
public string Text { get; }
|
||||
|
||||
public ILOpCodeLog(string text)
|
||||
{
|
||||
_text = text;
|
||||
Text = text;
|
||||
}
|
||||
|
||||
public void Emit(ILMethodBuilder context)
|
||||
{
|
||||
context.Generator.EmitWriteLine(_text);
|
||||
context.Generator.EmitWriteLine(Text);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -5,28 +5,28 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
struct ILOpCodeStore : IILEmit
|
||||
{
|
||||
public int Index { get; private set; }
|
||||
public int Index { get; }
|
||||
|
||||
public IoType IoType { get; private set; }
|
||||
public VarType VarType { get; }
|
||||
|
||||
public RegisterSize RegisterSize { get; private set; }
|
||||
public RegisterSize RegisterSize { get; }
|
||||
|
||||
public ILOpCodeStore(int index, IoType ioType, RegisterSize registerSize = 0)
|
||||
public ILOpCodeStore(int index, VarType varType, RegisterSize registerSize = 0)
|
||||
{
|
||||
Index = index;
|
||||
IoType = ioType;
|
||||
VarType = varType;
|
||||
RegisterSize = registerSize;
|
||||
}
|
||||
|
||||
public void Emit(ILMethodBuilder context)
|
||||
{
|
||||
switch (IoType)
|
||||
switch (VarType)
|
||||
{
|
||||
case IoType.Arg: context.Generator.EmitStarg(Index); break;
|
||||
case VarType.Arg: context.Generator.EmitStarg(Index); break;
|
||||
|
||||
case IoType.Flag: EmitStloc(context, Index, RegisterType.Flag); break;
|
||||
case IoType.Int: EmitStloc(context, Index, RegisterType.Int); break;
|
||||
case IoType.Vector: EmitStloc(context, Index, RegisterType.Vector); break;
|
||||
case VarType.Flag: EmitStloc(context, Index, RegisterType.Flag); break;
|
||||
case VarType.Int: EmitStloc(context, Index, RegisterType.Int); break;
|
||||
case VarType.Vector: EmitStloc(context, Index, RegisterType.Vector); break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -7,15 +7,33 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
private ILBlock _block;
|
||||
|
||||
public ILOpCodeStoreState(ILBlock block)
|
||||
private TranslatedSub _callSub;
|
||||
|
||||
public ILOpCodeStoreState(ILBlock block, TranslatedSub callSub = null)
|
||||
{
|
||||
_block = block;
|
||||
_block = block;
|
||||
_callSub = callSub;
|
||||
}
|
||||
|
||||
public void Emit(ILMethodBuilder context)
|
||||
{
|
||||
long intOutputs = context.LocalAlloc.GetIntOutputs(_block);
|
||||
long vecOutputs = context.LocalAlloc.GetVecOutputs(_block);
|
||||
long intOutputs = context.RegUsage.GetIntOutputs(_block);
|
||||
long vecOutputs = context.RegUsage.GetVecOutputs(_block);
|
||||
|
||||
if (Optimizations.AssumeStrictAbiCompliance && context.IsSubComplete)
|
||||
{
|
||||
intOutputs = RegisterUsage.ClearCallerSavedIntRegs(intOutputs, context.IsAarch64);
|
||||
vecOutputs = RegisterUsage.ClearCallerSavedVecRegs(vecOutputs, context.IsAarch64);
|
||||
}
|
||||
|
||||
if (_callSub != null)
|
||||
{
|
||||
//Those register are assigned on the callee function, without
|
||||
//reading it's value first. We don't need to write them because
|
||||
//they are not going to be read on the callee.
|
||||
intOutputs &= ~_callSub.IntNiRegsMask;
|
||||
vecOutputs &= ~_callSub.VecNiRegsMask;
|
||||
}
|
||||
|
||||
StoreLocals(context, intOutputs, RegisterType.Int);
|
||||
StoreLocals(context, vecOutputs, RegisterType.Vector);
|
||||
|
|
|
|||
|
|
@ -3,8 +3,13 @@ using System.Collections.Generic;
|
|||
|
||||
namespace ChocolArm64.Translation
|
||||
{
|
||||
class LocalAlloc
|
||||
class RegisterUsage
|
||||
{
|
||||
public const long CallerSavedIntRegistersMask = 0x7fL << 9;
|
||||
public const long PStateNzcvFlagsMask = 0xfL << 60;
|
||||
|
||||
public const long CallerSavedVecRegistersMask = 0xffffL << 16;
|
||||
|
||||
private class PathIo
|
||||
{
|
||||
private Dictionary<ILBlock, long> _allInputs;
|
||||
|
|
@ -18,31 +23,30 @@ namespace ChocolArm64.Translation
|
|||
_cmnOutputs = new Dictionary<ILBlock, long>();
|
||||
}
|
||||
|
||||
public PathIo(ILBlock root, long inputs, long outputs) : this()
|
||||
public void Set(ILBlock entry, long inputs, long outputs)
|
||||
{
|
||||
Set(root, inputs, outputs);
|
||||
}
|
||||
|
||||
public void Set(ILBlock root, long inputs, long outputs)
|
||||
{
|
||||
if (!_allInputs.TryAdd(root, inputs))
|
||||
if (!_allInputs.TryAdd(entry, inputs))
|
||||
{
|
||||
_allInputs[root] |= inputs;
|
||||
_allInputs[entry] |= inputs;
|
||||
}
|
||||
|
||||
if (!_cmnOutputs.TryAdd(root, outputs))
|
||||
if (!_cmnOutputs.TryAdd(entry, outputs))
|
||||
{
|
||||
_cmnOutputs[root] &= outputs;
|
||||
_cmnOutputs[entry] &= outputs;
|
||||
}
|
||||
|
||||
_allOutputs |= outputs;
|
||||
}
|
||||
|
||||
public long GetInputs(ILBlock root)
|
||||
public long GetInputs(ILBlock entry)
|
||||
{
|
||||
if (_allInputs.TryGetValue(root, out long inputs))
|
||||
if (_allInputs.TryGetValue(entry, out long inputs))
|
||||
{
|
||||
return inputs | (_allOutputs & ~_cmnOutputs[root]);
|
||||
//We also need to read the registers that may not be written
|
||||
//by all paths that can reach a exit point, to ensure that
|
||||
//the local variable will not remain uninitialized depending
|
||||
//on the flow path taken.
|
||||
return inputs | (_allOutputs & ~_cmnOutputs[entry]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -57,15 +61,38 @@ namespace ChocolArm64.Translation
|
|||
private Dictionary<ILBlock, PathIo> _intPaths;
|
||||
private Dictionary<ILBlock, PathIo> _vecPaths;
|
||||
|
||||
private struct BlockIo
|
||||
private struct BlockIo : IEquatable<BlockIo>
|
||||
{
|
||||
public ILBlock Block;
|
||||
public ILBlock Entry;
|
||||
public ILBlock Block { get; }
|
||||
public ILBlock Entry { get; }
|
||||
|
||||
public long IntInputs;
|
||||
public long VecInputs;
|
||||
public long IntOutputs;
|
||||
public long VecOutputs;
|
||||
public long IntInputs { get; set; }
|
||||
public long VecInputs { get; set; }
|
||||
public long IntOutputs { get; set; }
|
||||
public long VecOutputs { get; set; }
|
||||
|
||||
public BlockIo(ILBlock block, ILBlock entry)
|
||||
{
|
||||
Block = block;
|
||||
Entry = entry;
|
||||
|
||||
IntInputs = IntOutputs = 0;
|
||||
VecInputs = VecOutputs = 0;
|
||||
}
|
||||
|
||||
public BlockIo(
|
||||
ILBlock block,
|
||||
ILBlock entry,
|
||||
long intInputs,
|
||||
long vecInputs,
|
||||
long intOutputs,
|
||||
long vecOutputs) : this(block, entry)
|
||||
{
|
||||
IntInputs = intInputs;
|
||||
VecInputs = vecInputs;
|
||||
IntOutputs = intOutputs;
|
||||
VecOutputs = vecOutputs;
|
||||
}
|
||||
|
||||
public override bool Equals(object obj)
|
||||
{
|
||||
|
|
@ -74,6 +101,11 @@ namespace ChocolArm64.Translation
|
|||
return false;
|
||||
}
|
||||
|
||||
return Equals(other);
|
||||
}
|
||||
|
||||
public bool Equals(BlockIo other)
|
||||
{
|
||||
return other.Block == Block &&
|
||||
other.Entry == Entry &&
|
||||
other.IntInputs == IntInputs &&
|
||||
|
|
@ -98,25 +130,13 @@ namespace ChocolArm64.Translation
|
|||
}
|
||||
}
|
||||
|
||||
private const int MaxOptGraphLength = 40;
|
||||
|
||||
public LocalAlloc(ILBlock[] graph, ILBlock entry)
|
||||
public RegisterUsage()
|
||||
{
|
||||
_intPaths = new Dictionary<ILBlock, PathIo>();
|
||||
_vecPaths = new Dictionary<ILBlock, PathIo>();
|
||||
|
||||
if (graph.Length > 1 &&
|
||||
graph.Length < MaxOptGraphLength)
|
||||
{
|
||||
InitializeOptimal(graph, entry);
|
||||
}
|
||||
else
|
||||
{
|
||||
InitializeFast(graph);
|
||||
}
|
||||
}
|
||||
|
||||
private void InitializeOptimal(ILBlock[] graph, ILBlock entry)
|
||||
public void BuildUses(ILBlock entry)
|
||||
{
|
||||
//This will go through all possible paths on the graph,
|
||||
//and store all inputs/outputs for each block. A register
|
||||
|
|
@ -124,7 +144,7 @@ namespace ChocolArm64.Translation
|
|||
//When a block can be reached by more than one path, then the
|
||||
//output from all paths needs to be set for this block, and
|
||||
//only outputs present in all of the parent blocks can be considered
|
||||
//when doing input elimination. Each block chain have a entry, that's where
|
||||
//when doing input elimination. Each block chain has a entry, that's where
|
||||
//the code starts executing. They are present on the subroutine start point,
|
||||
//and on call return points too (address written to X30 by BL).
|
||||
HashSet<BlockIo> visited = new HashSet<BlockIo>();
|
||||
|
|
@ -133,19 +153,13 @@ namespace ChocolArm64.Translation
|
|||
|
||||
void Enqueue(BlockIo block)
|
||||
{
|
||||
if (!visited.Contains(block))
|
||||
if (visited.Add(block))
|
||||
{
|
||||
unvisited.Enqueue(block);
|
||||
|
||||
visited.Add(block);
|
||||
}
|
||||
}
|
||||
|
||||
Enqueue(new BlockIo()
|
||||
{
|
||||
Block = entry,
|
||||
Entry = entry
|
||||
});
|
||||
Enqueue(new BlockIo(entry, entry));
|
||||
|
||||
while (unvisited.Count > 0)
|
||||
{
|
||||
|
|
@ -177,19 +191,21 @@ namespace ChocolArm64.Translation
|
|||
|
||||
void EnqueueFromCurrent(ILBlock block, bool retTarget)
|
||||
{
|
||||
BlockIo blockIo = new BlockIo() { Block = block };
|
||||
BlockIo blockIo;
|
||||
|
||||
if (retTarget)
|
||||
{
|
||||
blockIo.Entry = block;
|
||||
blockIo = new BlockIo(block, block);
|
||||
}
|
||||
else
|
||||
{
|
||||
blockIo.Entry = current.Entry;
|
||||
blockIo.IntInputs = current.IntInputs;
|
||||
blockIo.VecInputs = current.VecInputs;
|
||||
blockIo.IntOutputs = current.IntOutputs;
|
||||
blockIo.VecOutputs = current.VecOutputs;
|
||||
blockIo = new BlockIo(
|
||||
block,
|
||||
current.Entry,
|
||||
current.IntInputs,
|
||||
current.VecInputs,
|
||||
current.IntOutputs,
|
||||
current.VecOutputs);
|
||||
}
|
||||
|
||||
Enqueue(blockIo);
|
||||
|
|
@ -207,54 +223,63 @@ namespace ChocolArm64.Translation
|
|||
}
|
||||
}
|
||||
|
||||
private void InitializeFast(ILBlock[] graph)
|
||||
{
|
||||
//This is WAY faster than InitializeOptimal, but results in
|
||||
//unneeded loads and stores, so the resulting code will be slower.
|
||||
long intInputs = 0, intOutputs = 0;
|
||||
long vecInputs = 0, vecOutputs = 0;
|
||||
public long GetIntInputs(ILBlock entry) => GetInputsImpl(entry, _intPaths.Values);
|
||||
public long GetVecInputs(ILBlock entry) => GetInputsImpl(entry, _vecPaths.Values);
|
||||
|
||||
foreach (ILBlock block in graph)
|
||||
{
|
||||
intInputs |= block.IntInputs;
|
||||
intOutputs |= block.IntOutputs;
|
||||
vecInputs |= block.VecInputs;
|
||||
vecOutputs |= block.VecOutputs;
|
||||
}
|
||||
|
||||
//It's possible that not all code paths writes to those output registers,
|
||||
//in those cases if we attempt to write an output registers that was
|
||||
//not written, we will be just writing zero and messing up the old register value.
|
||||
//So we just need to ensure that all outputs are loaded.
|
||||
if (graph.Length > 1)
|
||||
{
|
||||
intInputs |= intOutputs;
|
||||
vecInputs |= vecOutputs;
|
||||
}
|
||||
|
||||
foreach (ILBlock block in graph)
|
||||
{
|
||||
_intPaths.Add(block, new PathIo(block, intInputs, intOutputs));
|
||||
_vecPaths.Add(block, new PathIo(block, vecInputs, vecOutputs));
|
||||
}
|
||||
}
|
||||
|
||||
public long GetIntInputs(ILBlock root) => GetInputsImpl(root, _intPaths.Values);
|
||||
public long GetVecInputs(ILBlock root) => GetInputsImpl(root, _vecPaths.Values);
|
||||
|
||||
private long GetInputsImpl(ILBlock root, IEnumerable<PathIo> values)
|
||||
private long GetInputsImpl(ILBlock entry, IEnumerable<PathIo> values)
|
||||
{
|
||||
long inputs = 0;
|
||||
|
||||
foreach (PathIo path in values)
|
||||
{
|
||||
inputs |= path.GetInputs(root);
|
||||
inputs |= path.GetInputs(entry);
|
||||
}
|
||||
|
||||
return inputs;
|
||||
}
|
||||
|
||||
public long GetIntNotInputs(ILBlock entry) => GetNotInputsImpl(entry, _intPaths.Values);
|
||||
public long GetVecNotInputs(ILBlock entry) => GetNotInputsImpl(entry, _vecPaths.Values);
|
||||
|
||||
private long GetNotInputsImpl(ILBlock entry, IEnumerable<PathIo> values)
|
||||
{
|
||||
//Returns a mask with registers that are written to
|
||||
//before being read. Only those registers that are
|
||||
//written in all paths, and is not read before being
|
||||
//written to on those paths, should be set on the mask.
|
||||
long mask = -1L;
|
||||
|
||||
foreach (PathIo path in values)
|
||||
{
|
||||
mask &= path.GetOutputs() & ~path.GetInputs(entry);
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
public long GetIntOutputs(ILBlock block) => _intPaths[block].GetOutputs();
|
||||
public long GetVecOutputs(ILBlock block) => _vecPaths[block].GetOutputs();
|
||||
|
||||
public static long ClearCallerSavedIntRegs(long mask, bool isAarch64)
|
||||
{
|
||||
//TODO: ARM32 support.
|
||||
if (isAarch64)
|
||||
{
|
||||
mask &= ~(CallerSavedIntRegistersMask | PStateNzcvFlagsMask);
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
public static long ClearCallerSavedVecRegs(long mask, bool isAarch64)
|
||||
{
|
||||
//TODO: ARM32 support.
|
||||
if (isAarch64)
|
||||
{
|
||||
mask &= ~CallerSavedVecRegistersMask;
|
||||
}
|
||||
|
||||
return mask;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -10,21 +10,41 @@ namespace ChocolArm64.Translation
|
|||
|
||||
class TranslatedSub
|
||||
{
|
||||
//This is the minimum amount of calls needed for the method
|
||||
//to be retranslated with higher quality code. It's only worth
|
||||
//doing that for hot code.
|
||||
private const int MinCallCountForOpt = 30;
|
||||
|
||||
public ArmSubroutine Delegate { get; private set; }
|
||||
|
||||
public static int StateArgIdx { get; private set; }
|
||||
public static int MemoryArgIdx { get; private set; }
|
||||
public static int StateArgIdx { get; }
|
||||
public static int MemoryArgIdx { get; }
|
||||
|
||||
public static Type[] FixedArgTypes { get; private set; }
|
||||
public static Type[] FixedArgTypes { get; }
|
||||
|
||||
public DynamicMethod Method { get; private set; }
|
||||
public DynamicMethod Method { get; }
|
||||
|
||||
public TranslationTier Tier { get; private set; }
|
||||
public TranslationTier Tier { get; }
|
||||
|
||||
public TranslatedSub(DynamicMethod method, TranslationTier tier)
|
||||
public long IntNiRegsMask { get; }
|
||||
public long VecNiRegsMask { get; }
|
||||
|
||||
private bool _isWorthOptimizing;
|
||||
|
||||
private int _callCount;
|
||||
|
||||
public TranslatedSub(
|
||||
DynamicMethod method,
|
||||
long intNiRegsMask,
|
||||
long vecNiRegsMask,
|
||||
TranslationTier tier,
|
||||
bool isWorthOptimizing)
|
||||
{
|
||||
Method = method ?? throw new ArgumentNullException(nameof(method));;
|
||||
Tier = tier;
|
||||
Method = method ?? throw new ArgumentNullException(nameof(method));;
|
||||
IntNiRegsMask = intNiRegsMask;
|
||||
VecNiRegsMask = vecNiRegsMask;
|
||||
_isWorthOptimizing = isWorthOptimizing;
|
||||
Tier = tier;
|
||||
}
|
||||
|
||||
static TranslatedSub()
|
||||
|
|
@ -61,5 +81,24 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
return Delegate(threadState, memory);
|
||||
}
|
||||
|
||||
public bool IsWorthOptimizing()
|
||||
{
|
||||
if (!_isWorthOptimizing)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
if (_callCount++ < MinCallCountForOpt)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
//Only return true once, so that it is
|
||||
//added to the queue only once.
|
||||
_isWorthOptimizing = false;
|
||||
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -63,48 +63,36 @@ namespace ChocolArm64.Translation
|
|||
CpuTrace?.Invoke(this, new CpuTraceEventArgs(position));
|
||||
}
|
||||
|
||||
TranslatedSub subroutine = GetOrTranslateSubroutine(state, position);
|
||||
if (!_cache.TryGetSubroutine(position, out TranslatedSub sub))
|
||||
{
|
||||
sub = TranslateLowCq(position, state.GetExecutionMode());
|
||||
}
|
||||
|
||||
position = subroutine.Execute(state, _memory);
|
||||
position = sub.Execute(state, _memory);
|
||||
}
|
||||
while (position != 0 && state.Running);
|
||||
|
||||
state.CurrentTranslator = null;
|
||||
}
|
||||
|
||||
internal void TranslateVirtualSubroutine(CpuThreadState state, long position)
|
||||
{
|
||||
if (!_cache.TryGetSubroutine(position, out TranslatedSub sub) || sub.Tier == TranslationTier.Tier0)
|
||||
{
|
||||
_queue.Enqueue(new TranslatorQueueItem(position, state.GetExecutionMode(), TranslationTier.Tier1));
|
||||
}
|
||||
}
|
||||
|
||||
internal ArmSubroutine GetOrTranslateVirtualSubroutine(CpuThreadState state, long position)
|
||||
internal ArmSubroutine GetOrTranslateSubroutine(CpuThreadState state, long position, CallType cs)
|
||||
{
|
||||
if (!_cache.TryGetSubroutine(position, out TranslatedSub sub))
|
||||
{
|
||||
sub = TranslateLowCq(position, state.GetExecutionMode());
|
||||
}
|
||||
|
||||
if (sub.Tier == TranslationTier.Tier0)
|
||||
if (sub.IsWorthOptimizing())
|
||||
{
|
||||
_queue.Enqueue(new TranslatorQueueItem(position, state.GetExecutionMode(), TranslationTier.Tier1));
|
||||
bool isComplete = cs == CallType.Call ||
|
||||
cs == CallType.VirtualCall;
|
||||
|
||||
_queue.Enqueue(position, state.GetExecutionMode(), TranslationTier.Tier1, isComplete);
|
||||
}
|
||||
|
||||
return sub.Delegate;
|
||||
}
|
||||
|
||||
internal TranslatedSub GetOrTranslateSubroutine(CpuThreadState state, long position)
|
||||
{
|
||||
if (!_cache.TryGetSubroutine(position, out TranslatedSub subroutine))
|
||||
{
|
||||
subroutine = TranslateLowCq(position, state.GetExecutionMode());
|
||||
}
|
||||
|
||||
return subroutine;
|
||||
}
|
||||
|
||||
private void TranslateQueuedSubs()
|
||||
{
|
||||
while (_threadCount != 0)
|
||||
|
|
@ -124,7 +112,7 @@ namespace ChocolArm64.Translation
|
|||
}
|
||||
else
|
||||
{
|
||||
TranslateHighCq(item.Position, item.Mode);
|
||||
TranslateHighCq(item.Position, item.Mode, item.IsComplete);
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -142,14 +130,16 @@ namespace ChocolArm64.Translation
|
|||
|
||||
string subName = GetSubroutineName(position);
|
||||
|
||||
ILMethodBuilder ilMthdBuilder = new ILMethodBuilder(context.GetILBlocks(), subName);
|
||||
bool isAarch64 = mode == ExecutionMode.Aarch64;
|
||||
|
||||
TranslatedSub subroutine = ilMthdBuilder.GetSubroutine(TranslationTier.Tier0);
|
||||
ILMethodBuilder ilMthdBuilder = new ILMethodBuilder(context.GetILBlocks(), subName, isAarch64);
|
||||
|
||||
TranslatedSub subroutine = ilMthdBuilder.GetSubroutine(TranslationTier.Tier0, isWorthOptimizing: true);
|
||||
|
||||
return _cache.GetOrAdd(position, subroutine, block.OpCodes.Count);
|
||||
}
|
||||
|
||||
private void TranslateHighCq(long position, ExecutionMode mode)
|
||||
private TranslatedSub TranslateHighCq(long position, ExecutionMode mode, bool isComplete)
|
||||
{
|
||||
Block graph = Decoder.DecodeSubroutine(_memory, position, mode);
|
||||
|
||||
|
|
@ -159,9 +149,13 @@ namespace ChocolArm64.Translation
|
|||
|
||||
string subName = GetSubroutineName(position);
|
||||
|
||||
ILMethodBuilder ilMthdBuilder = new ILMethodBuilder(ilBlocks, subName);
|
||||
bool isAarch64 = mode == ExecutionMode.Aarch64;
|
||||
|
||||
TranslatedSub subroutine = ilMthdBuilder.GetSubroutine(TranslationTier.Tier1);
|
||||
isComplete &= !context.HasIndirectJump;
|
||||
|
||||
ILMethodBuilder ilMthdBuilder = new ILMethodBuilder(ilBlocks, subName, isAarch64, isComplete);
|
||||
|
||||
TranslatedSub subroutine = ilMthdBuilder.GetSubroutine(TranslationTier.Tier1, context.HasSlowCall);
|
||||
|
||||
int ilOpCount = 0;
|
||||
|
||||
|
|
@ -170,9 +164,11 @@ namespace ChocolArm64.Translation
|
|||
ilOpCount += ilBlock.Count;
|
||||
}
|
||||
|
||||
ForceAheadOfTimeCompilation(subroutine);
|
||||
|
||||
_cache.AddOrUpdate(position, subroutine, ilOpCount);
|
||||
|
||||
ForceAheadOfTimeCompilation(subroutine);
|
||||
return subroutine;
|
||||
}
|
||||
|
||||
private string GetSubroutineName(long position)
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
using ChocolArm64.State;
|
||||
using System.Collections.Concurrent;
|
||||
using System.Threading;
|
||||
|
||||
|
|
@ -5,10 +6,6 @@ namespace ChocolArm64.Translation
|
|||
{
|
||||
class TranslatorQueue
|
||||
{
|
||||
//This is the maximum number of functions to be translated that the queue can hold.
|
||||
//The value may need some tuning to find the sweet spot.
|
||||
private const int MaxQueueSize = 1024;
|
||||
|
||||
private ConcurrentStack<TranslatorQueueItem>[] _translationQueue;
|
||||
|
||||
private ManualResetEvent _queueDataReceivedEvent;
|
||||
|
|
@ -27,14 +24,11 @@ namespace ChocolArm64.Translation
|
|||
_queueDataReceivedEvent = new ManualResetEvent(false);
|
||||
}
|
||||
|
||||
public void Enqueue(TranslatorQueueItem item)
|
||||
public void Enqueue(long position, ExecutionMode mode, TranslationTier tier, bool isComplete)
|
||||
{
|
||||
ConcurrentStack<TranslatorQueueItem> queue = _translationQueue[(int)item.Tier];
|
||||
TranslatorQueueItem item = new TranslatorQueueItem(position, mode, tier, isComplete);
|
||||
|
||||
if (queue.Count >= MaxQueueSize)
|
||||
{
|
||||
queue.TryPop(out _);
|
||||
}
|
||||
ConcurrentStack<TranslatorQueueItem> queue = _translationQueue[(int)tier];
|
||||
|
||||
queue.Push(item);
|
||||
|
||||
|
|
|
|||
|
|
@ -10,11 +10,18 @@ namespace ChocolArm64.Translation
|
|||
|
||||
public TranslationTier Tier { get; }
|
||||
|
||||
public TranslatorQueueItem(long position, ExecutionMode mode, TranslationTier tier)
|
||||
public bool IsComplete { get; }
|
||||
|
||||
public TranslatorQueueItem(
|
||||
long position,
|
||||
ExecutionMode mode,
|
||||
TranslationTier tier,
|
||||
bool isComplete = false)
|
||||
{
|
||||
Position = position;
|
||||
Mode = mode;
|
||||
Tier = tier;
|
||||
Position = position;
|
||||
Mode = mode;
|
||||
Tier = tier;
|
||||
IsComplete = isComplete;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
namespace ChocolArm64.Translation
|
||||
{
|
||||
enum IoType
|
||||
enum VarType
|
||||
{
|
||||
Arg,
|
||||
Flag,
|
||||
Loading…
Reference in a new issue