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Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction)

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This commit is contained in:
gdkchan 2018-03-30 17:37:31 -03:00
parent 94b3eb96a9
commit 6cb940049d
3 changed files with 21 additions and 12 deletions
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6
Instruction/AInstEmitSimdArithmetic.cs
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@ -548,12 +548,12 @@ namespace ChocolArm64.Instruction
public static void Uabd_V(AILEmitterCtx Context)
{
EmitVectorTernaryOpZx(Context, () => EmitAbd(Context));
EmitVectorBinaryOpZx(Context, () => EmitAbd(Context));
}
public static void Uabdl_V(AILEmitterCtx Context)
{
EmitVectorWidenRnRmTernaryOpZx(Context, () => EmitAbd(Context));
EmitVectorWidenRnRmBinaryOpZx(Context, () => EmitAbd(Context));
}
private static void EmitAbd(AILEmitterCtx Context)
@ -563,8 +563,6 @@ namespace ChocolArm64.Instruction
Type[] Types = new Type[] { typeof(long) };
Context.EmitCall(typeof(Math).GetMethod(nameof(Math.Abs), Types));
Context.Emit(OpCodes.Add);
}
public static void Uaddl_V(AILEmitterCtx Context)

6
Instruction/AInstEmitSimdHelper.cs
View file

@ -447,6 +447,9 @@ namespace ChocolArm64.Instruction
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
Context.EmitLdvec(Op.Rd);
Context.EmitStvectmp();
int Elems = 8 >> Op.Size;
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
@ -489,6 +492,9 @@ namespace ChocolArm64.Instruction
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
Context.EmitLdvec(Op.Rd);
Context.EmitStvectmp();
int Elems = 8 >> Op.Size;
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;

19
Instruction/AInstEmitSimdMove.cs
View file

@ -61,6 +61,9 @@ namespace ChocolArm64.Instruction
{
AOpCodeSimdExt Op = (AOpCodeSimdExt)Context.CurrOp;
Context.EmitLdvec(Op.Rd);
Context.EmitStvectmp();
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
int Position = Op.Imm4;
@ -75,10 +78,12 @@ namespace ChocolArm64.Instruction
}
EmitVectorExtractZx(Context, Reg, Position++, 0);
EmitVectorInsert(Context, Op.Rd, Index, 0);
EmitVectorInsertTmp(Context, Index, 0);
}
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
@ -113,7 +118,7 @@ namespace ChocolArm64.Instruction
EmitVectorExtractZx(Context, Op.Rn, 0, 3);
EmitIntZeroHigherIfNeeded(Context);
EmitIntZeroUpperIfNeeded(Context);
Context.EmitStintzr(Op.Rd);
}
@ -124,7 +129,7 @@ namespace ChocolArm64.Instruction
EmitVectorExtractZx(Context, Op.Rn, 1, 3);
EmitIntZeroHigherIfNeeded(Context);
EmitIntZeroUpperIfNeeded(Context);
Context.EmitStintzr(Op.Rd);
}
@ -135,7 +140,7 @@ namespace ChocolArm64.Instruction
Context.EmitLdintzr(Op.Rn);
EmitIntZeroHigherIfNeeded(Context);
EmitIntZeroUpperIfNeeded(Context);
EmitScalarSet(Context, Op.Rd, 3);
}
@ -146,7 +151,7 @@ namespace ChocolArm64.Instruction
Context.EmitLdintzr(Op.Rn);
EmitIntZeroHigherIfNeeded(Context);
EmitIntZeroUpperIfNeeded(Context);
EmitVectorInsert(Context, Op.Rd, 1, 3);
}
@ -301,7 +306,7 @@ namespace ChocolArm64.Instruction
EmitVectorZip(Context, Part: 1);
}
private static void EmitIntZeroHigherIfNeeded(AILEmitterCtx Context)
private static void EmitIntZeroUpperIfNeeded(AILEmitterCtx Context)
{
if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
{