forked from suyu/suyu
shader: Implement SEL
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parent
726625cf50
commit
8810c88b7e
4 changed files with 53 additions and 16 deletions
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@ -79,6 +79,7 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/move_register.cpp
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frontend/maxwell/translate/impl/move_register.cpp
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frontend/maxwell/translate/impl/move_special_register.cpp
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frontend/maxwell/translate/impl/move_special_register.cpp
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frontend/maxwell/translate/impl/not_implemented.cpp
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frontend/maxwell/translate/impl/not_implemented.cpp
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frontend/maxwell/translate/impl/select_source_with_predicate.cpp
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frontend/maxwell/translate/translate.cpp
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frontend/maxwell/translate/translate.cpp
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frontend/maxwell/translate/translate.h
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frontend/maxwell/translate/translate.h
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ir_opt/collect_shader_info_pass.cpp
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ir_opt/collect_shader_info_pass.cpp
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@ -729,18 +729,6 @@ void TranslatorVisitor::SAM(u64) {
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ThrowNotImplemented(Opcode::SAM);
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ThrowNotImplemented(Opcode::SAM);
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}
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}
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void TranslatorVisitor::SEL_reg(u64) {
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ThrowNotImplemented(Opcode::SEL_reg);
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}
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void TranslatorVisitor::SEL_cbuf(u64) {
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ThrowNotImplemented(Opcode::SEL_cbuf);
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}
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void TranslatorVisitor::SEL_imm(u64) {
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ThrowNotImplemented(Opcode::SEL_imm);
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}
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void TranslatorVisitor::SETCRSPTR(u64) {
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void TranslatorVisitor::SETCRSPTR(u64) {
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ThrowNotImplemented(Opcode::SETCRSPTR);
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ThrowNotImplemented(Opcode::SETCRSPTR);
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}
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}
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@ -0,0 +1,44 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void SEL(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> op_a;
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BitField<39, 3, IR::Pred> pred;
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BitField<42, 1, u64> neg_pred;
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} const sel{insn};
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const IR::U1 pred = v.ir.GetPred(sel.pred);
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IR::U32 op_a{v.X(sel.op_a)};
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IR::U32 op_b{src};
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if (sel.neg_pred != 0) {
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std::swap(op_a, op_b);
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}
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const IR::U32 result{v.ir.Select(pred, op_a, op_b)};
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v.X(sel.dest_reg, result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::SEL_reg(u64 insn) {
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SEL(*this, insn, GetReg20(insn));
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}
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void TranslatorVisitor::SEL_cbuf(u64 insn) {
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SEL(*this, insn, GetCbuf(insn));
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}
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void TranslatorVisitor::SEL_imm(u64 insn) {
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SEL(*this, insn, GetImm20(insn));
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}
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} // namespace Shader::Maxwell
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@ -109,11 +109,13 @@ IR::Opcode UndefOpcode(const FlagTag&) noexcept {
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class Pass {
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class Pass {
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public:
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public:
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void WriteVariable(auto variable, IR::Block* block, const IR::Value& value) {
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template <typename Type>
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void WriteVariable(Type variable, IR::Block* block, const IR::Value& value) {
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current_def[variable].insert_or_assign(block, value);
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current_def[variable].insert_or_assign(block, value);
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}
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}
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IR::Value ReadVariable(auto variable, IR::Block* block) {
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template <typename Type>
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IR::Value ReadVariable(Type variable, IR::Block* block) {
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const ValueMap& def{current_def[variable]};
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const ValueMap& def{current_def[variable]};
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if (const auto it{def.find(block)}; it != def.end()) {
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if (const auto it{def.find(block)}; it != def.end()) {
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return it->second;
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return it->second;
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@ -132,7 +134,8 @@ public:
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}
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}
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private:
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private:
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IR::Value ReadVariableRecursive(auto variable, IR::Block* block) {
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template <typename Type>
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IR::Value ReadVariableRecursive(Type variable, IR::Block* block) {
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IR::Value val;
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IR::Value val;
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if (!sealed_blocks.contains(block)) {
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if (!sealed_blocks.contains(block)) {
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// Incomplete CFG
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// Incomplete CFG
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@ -154,7 +157,8 @@ private:
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return val;
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return val;
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}
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}
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IR::Value AddPhiOperands(auto variable, IR::Inst& phi, IR::Block* block) {
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template <typename Type>
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IR::Value AddPhiOperands(Type variable, IR::Inst& phi, IR::Block* block) {
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for (IR::Block* const imm_pred : block->ImmediatePredecessors()) {
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for (IR::Block* const imm_pred : block->ImmediatePredecessors()) {
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phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred));
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phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred));
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}
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}
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