forked from suyu/suyu
Merge pull request #706 from lioncash/unused
dyncom: Remove more unused/unnecessary code
This commit is contained in:
commit
4dbe358a71
5 changed files with 1 additions and 95 deletions
src/core
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@ -31,7 +31,6 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
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// Reset the core to initial state
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ARMul_Reset(state.get());
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state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
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state->Emulate = RUN;
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// Switch to the desired privilege mode.
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@ -99,7 +98,6 @@ void ARM_DynCom::ResetContext(Core::ThreadContext& context, u32 stack_top, u32 e
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context.pc = entry_point;
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context.sp = stack_top;
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context.cpsr = 0x1F; // Usermode
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context.mode = 8; // Instructs dyncom CPU core to start execution as if it's "resuming" a thread.
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}
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void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
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@ -113,8 +111,6 @@ void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
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ctx.fpscr = state->VFP[1];
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ctx.fpexc = state->VFP[2];
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ctx.mode = state->NextInstr;
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}
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void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
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@ -128,8 +124,6 @@ void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
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state->VFP[1] = ctx.fpscr;
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state->VFP[2] = ctx.fpexc;
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state->NextInstr = ctx.mode;
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}
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void ARM_DynCom::PrepareReschedule() {
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@ -29,22 +29,8 @@ ARMul_State* ARMul_NewState(ARMul_State* state)
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memset(state, 0, sizeof(ARMul_State));
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state->Emulate = RUN;
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for (unsigned int i = 0; i < 16; i++) {
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state->Reg[i] = 0;
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for (unsigned int j = 0; j < 7; j++)
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state->RegBank[j][i] = 0;
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}
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for (unsigned int i = 0; i < 7; i++)
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state->Spsr[i] = 0;
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state->Mode = USER32MODE;
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state->VectorCatch = 0;
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state->Aborted = false;
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state->Reseted = false;
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state->Inted = 3;
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state->LastInted = 3;
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state->lateabtSig = HIGH;
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state->bigendSig = LOW;
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@ -129,26 +115,18 @@ void ARMul_Reset(ARMul_State* state)
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{
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VFPInit(state);
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state->NextInstr = 0;
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state->Reg[15] = 0;
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state->Cpsr = INTBITS | SVC32MODE;
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state->Mode = SVC32MODE;
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state->Bank = SVCBANK;
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FLUSHPIPE;
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ResetMPCoreCP15Registers(state);
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state->EndCondition = 0;
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state->ErrorCode = 0;
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state->NresetSig = HIGH;
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state->NfiqSig = HIGH;
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state->NirqSig = HIGH;
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state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
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state->abortSig = LOW;
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state->AbortAddr = 1;
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state->NumInstrs = 0;
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}
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@ -53,14 +53,11 @@ typedef u64 ARMdword; // must be 64 bits wide
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typedef u32 ARMword; // must be 32 bits wide
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typedef u16 ARMhword; // must be 16 bits wide
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typedef u8 ARMbyte; // must be 8 bits wide
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typedef struct ARMul_State ARMul_State;
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#define VFP_REG_NUM 64
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struct ARMul_State
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{
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ARMword Emulate; // To start and stop emulation
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unsigned EndCondition; // Reason for stopping
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unsigned ErrorCode; // Type of illegal instruction
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// Order of the following register should not be modified
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ARMword Reg[16]; // The current register file
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@ -89,8 +86,6 @@ struct ARMul_State
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ARMword ExtReg[VFP_REG_NUM];
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/* ---- End of the ordered registers ---- */
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ARMword RegBank[7][16]; // all the registers
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ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed
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unsigned int shifter_carry_out;
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@ -102,10 +97,7 @@ struct ARMul_State
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unsigned long long NumInstrs; // The number of instructions executed
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unsigned NumInstrsToExecute;
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unsigned NextInstr;
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unsigned VectorCatch; // Caught exception mask
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unsigned NresetSig; // Reset the processor
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unsigned NresetSig; // Reset the processor
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unsigned NfiqSig;
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unsigned NirqSig;
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@ -147,13 +139,6 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
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*/
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unsigned lateabtSig;
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bool Aborted; // Sticky flag for aborts
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bool Reseted; // Sticky flag for Reset
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ARMword Inted, LastInted; // Sticky flags for interrupts
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ARMword Base; // Extra hand for base writeback
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ARMword AbortAddr; // To keep track of Prefetch aborts
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ARMword Vector; // Synthesize aborts in cycle modes
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// For differentiating ARM core emulaiton.
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bool is_v4; // Are we emulating a v4 architecture (or higher)?
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bool is_v5; // Are we emulating a v5 architecture?
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@ -167,14 +152,6 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
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// Added by ksh in 2005-10-1
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cpu_config_t* cpu;
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u32 CurrInstr;
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u32 last_pc; // The last PC executed
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u32 last_instr; // The last instruction executed
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u32 WriteAddr[17];
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u32 WriteData[17];
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u32 WritePc[17];
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u32 CurrWrite;
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};
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/***************************************************************************\
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@ -260,34 +237,6 @@ enum {
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ARMul_INC = 3
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};
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enum {
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ARMul_CP13_R0_FIQ = 0x1,
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ARMul_CP13_R0_IRQ = 0x2,
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ARMul_CP13_R8_PMUS = 0x1,
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ARMul_CP14_R0_ENABLE = 0x0001,
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ARMul_CP14_R0_CLKRST = 0x0004,
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ARMul_CP14_R0_CCD = 0x0008,
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ARMul_CP14_R0_INTEN0 = 0x0010,
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ARMul_CP14_R0_INTEN1 = 0x0020,
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ARMul_CP14_R0_INTEN2 = 0x0040,
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ARMul_CP14_R0_FLAG0 = 0x0100,
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ARMul_CP14_R0_FLAG1 = 0x0200,
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ARMul_CP14_R0_FLAG2 = 0x0400,
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ARMul_CP14_R10_MOE_IB = 0x0004,
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ARMul_CP14_R10_MOE_DB = 0x0008,
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ARMul_CP14_R10_MOE_BT = 0x000c,
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ARMul_CP15_R1_ENDIAN = 0x0080,
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ARMul_CP15_R1_ALIGN = 0x0002,
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ARMul_CP15_R5_X = 0x0400,
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ARMul_CP15_R5_ST_ALIGN = 0x0001,
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ARMul_CP15_R5_IMPRE = 0x0406,
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ARMul_CP15_R5_MMU_EXCPT = 0x0400,
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ARMul_CP15_DBCON_M = 0x0100,
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ARMul_CP15_DBCON_E1 = 0x000c,
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ARMul_CP15_DBCON_E0 = 0x0003
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};
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/***************************************************************************\
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* Definitons of things in the host environment *
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\***************************************************************************/
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@ -38,16 +38,6 @@ enum : u32 {
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INTBITS = 0x1C0,
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};
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// Different ways to start the next instruction.
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enum {
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SEQ = 0,
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NONSEQ = 1,
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PCINCEDSEQ = 2,
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PCINCEDNONSEQ = 3,
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PRIMEPIPE = 4,
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RESUME = 8
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};
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// Values for Emulate.
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enum {
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STOP = 0, // Stop
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@ -55,5 +45,3 @@ enum {
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ONCE = 2, // Execute just one interation
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RUN = 3 // Continuous execution
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};
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#define FLUSHPIPE state->NextInstr |= PRIMEPIPE
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@ -21,9 +21,6 @@ struct ThreadContext {
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u32 fpu_registers[32];
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u32 fpscr;
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u32 fpexc;
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// These are not part of native ThreadContext, but needed by emu
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u32 mode;
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};
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extern ARM_Interface* g_app_core; ///< ARM11 application core
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