579000e747
Register 0xE24 is actually a macro that sets some shader parameters in the register structure. Macros are uploaded to the GPU at startup and have their own ISA, we'll probably write an interpreter for this in the future.
106 lines
3.6 KiB
C++
106 lines
3.6 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "video_core/engines/maxwell_3d.h"
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namespace Tegra {
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namespace Engines {
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const std::unordered_map<u32, Maxwell3D::MethodInfo> Maxwell3D::method_handlers = {
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{0xE24, {"SetShader", 5, &Maxwell3D::SetShader}},
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};
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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void Maxwell3D::CallMethod(u32 method, const std::vector<u32>& parameters) {
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// TODO(Subv): Write an interpreter for the macros uploaded via registers 0x45 and 0x47
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auto itr = method_handlers.find(method);
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if (itr == method_handlers.end()) {
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LOG_ERROR(HW_GPU, "Unhandled method call %08X", method);
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return;
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}
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ASSERT(itr->second.arguments == parameters.size());
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(this->*itr->second.handler)(parameters);
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}
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void Maxwell3D::WriteReg(u32 method, u32 value) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid Maxwell3D register, increase the size of the Regs structure");
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regs.reg_array[method] = value;
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#define MAXWELL3D_REG_INDEX(field_name) (offsetof(Regs, field_name) / sizeof(u32))
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switch (method) {
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case MAXWELL3D_REG_INDEX(code_address.code_address_high):
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case MAXWELL3D_REG_INDEX(code_address.code_address_low): {
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// Note: For some reason games (like Puyo Puyo Tetris) seem to write 0 to the CODE_ADDRESS
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// register, we do not currently know if that's intended or a bug, so we assert it lest
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// stuff breaks in other places (like the shader address calculation).
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ASSERT_MSG(regs.code_address.CodeAddress() == 0, "Unexpected CODE_ADDRESS register value.");
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break;
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}
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case MAXWELL3D_REG_INDEX(draw.vertex_end_gl): {
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DrawArrays();
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break;
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}
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case MAXWELL3D_REG_INDEX(query.query_get): {
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ProcessQueryGet();
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break;
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}
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default:
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break;
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}
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#undef MAXWELL3D_REG_INDEX
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}
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void Maxwell3D::ProcessQueryGet() {
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GPUVAddr sequence_address = regs.query.QueryAddress();
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// Since the sequence address is given as a GPU VAddr, we have to convert it to an application
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// VAddr before writing.
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VAddr address = memory_manager.PhysicalToVirtualAddress(sequence_address);
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switch (regs.query.query_get.mode) {
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case Regs::QueryMode::Write: {
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// Write the current query sequence to the sequence address.
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u32 sequence = regs.query.query_sequence;
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Memory::Write32(address, sequence);
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Query mode %u not implemented", regs.query.query_get.mode.Value());
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}
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}
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void Maxwell3D::DrawArrays() {
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LOG_WARNING(HW_GPU, "Game requested a DrawArrays, ignoring");
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}
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void Maxwell3D::SetShader(const std::vector<u32>& parameters) {
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/**
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* Parameters description:
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* [0] = Shader Program.
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* [1] = Unknown.
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* [2] = Offset to the start of the shader, after the 0x30 bytes header.
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* [3] = Shader Type.
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* [4] = Const Buffer Address >> 8.
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*/
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auto shader_program = static_cast<Regs::ShaderProgram>(parameters[0]);
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// TODO(Subv): This address is probably an offset from the CODE_ADDRESS register.
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GPUVAddr address = parameters[2];
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auto shader_type = static_cast<Regs::ShaderType>(parameters[3]);
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GPUVAddr cb_address = parameters[4] << 8;
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auto& shader = state.shaders[static_cast<size_t>(shader_program)];
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shader.program = shader_program;
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shader.type = shader_type;
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shader.address = address;
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shader.cb_address = cb_address;
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}
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} // namespace Engines
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} // namespace Tegra
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