1efdb4897e
Given we already ensure nothing can set the zeroth register in SetRegister(), we don't need to check if the index is zero and special case it. We can just access the register normally, since it's already going to be zero. We can also replace the assertion with .at() to perform the equivalent behavior inline as part of the API.
270 lines
8.7 KiB
C++
270 lines
8.7 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/macro_interpreter.h"
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namespace Tegra {
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MacroInterpreter::MacroInterpreter(Engines::Maxwell3D& maxwell3d) : maxwell3d(maxwell3d) {}
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void MacroInterpreter::Execute(u32 offset, std::vector<u32> parameters) {
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Reset();
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registers[1] = parameters[0];
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this->parameters = std::move(parameters);
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// Execute the code until we hit an exit condition.
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bool keep_executing = true;
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while (keep_executing) {
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keep_executing = Step(offset, false);
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}
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// Assert the the macro used all the input parameters
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ASSERT(next_parameter_index == this->parameters.size());
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}
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void MacroInterpreter::Reset() {
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registers = {};
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pc = 0;
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delayed_pc = {};
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method_address.raw = 0;
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parameters.clear();
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// The next parameter index starts at 1, because $r1 already has the value of the first
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// parameter.
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next_parameter_index = 1;
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carry_flag = false;
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}
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bool MacroInterpreter::Step(u32 offset, bool is_delay_slot) {
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u32 base_address = pc;
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Opcode opcode = GetOpcode(offset);
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pc += 4;
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// Update the program counter if we were delayed
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if (delayed_pc) {
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ASSERT(is_delay_slot);
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pc = *delayed_pc;
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delayed_pc = {};
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}
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switch (opcode.operation) {
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case Operation::ALU: {
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u32 result = GetALUResult(opcode.alu_operation, GetRegister(opcode.src_a),
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GetRegister(opcode.src_b));
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ProcessResult(opcode.result_operation, opcode.dst, result);
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break;
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}
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case Operation::AddImmediate: {
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ProcessResult(opcode.result_operation, opcode.dst,
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GetRegister(opcode.src_a) + opcode.immediate);
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break;
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}
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case Operation::ExtractInsert: {
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u32 dst = GetRegister(opcode.src_a);
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u32 src = GetRegister(opcode.src_b);
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src = (src >> opcode.bf_src_bit) & opcode.GetBitfieldMask();
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dst &= ~(opcode.GetBitfieldMask() << opcode.bf_dst_bit);
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dst |= src << opcode.bf_dst_bit;
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ProcessResult(opcode.result_operation, opcode.dst, dst);
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break;
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}
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case Operation::ExtractShiftLeftImmediate: {
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u32 dst = GetRegister(opcode.src_a);
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u32 src = GetRegister(opcode.src_b);
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u32 result = ((src >> dst) & opcode.GetBitfieldMask()) << opcode.bf_dst_bit;
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ProcessResult(opcode.result_operation, opcode.dst, result);
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break;
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}
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case Operation::ExtractShiftLeftRegister: {
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u32 dst = GetRegister(opcode.src_a);
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u32 src = GetRegister(opcode.src_b);
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u32 result = ((src >> opcode.bf_src_bit) & opcode.GetBitfieldMask()) << dst;
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ProcessResult(opcode.result_operation, opcode.dst, result);
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break;
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}
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case Operation::Read: {
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u32 result = Read(GetRegister(opcode.src_a) + opcode.immediate);
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ProcessResult(opcode.result_operation, opcode.dst, result);
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break;
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}
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case Operation::Branch: {
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ASSERT_MSG(!is_delay_slot, "Executing a branch in a delay slot is not valid");
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u32 value = GetRegister(opcode.src_a);
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bool taken = EvaluateBranchCondition(opcode.branch_condition, value);
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if (taken) {
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// Ignore the delay slot if the branch has the annul bit.
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if (opcode.branch_annul) {
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pc = base_address + opcode.GetBranchTarget();
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return true;
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}
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delayed_pc = base_address + opcode.GetBranchTarget();
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// Execute one more instruction due to the delay slot.
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return Step(offset, true);
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}
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unimplemented macro operation {}",
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static_cast<u32>(opcode.operation.Value()));
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}
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if (opcode.is_exit) {
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// Exit has a delay slot, execute the next instruction
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// Note: Executing an exit during a branch delay slot will cause the instruction at the
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// branch target to be executed before exiting.
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Step(offset, true);
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return false;
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}
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return true;
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}
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MacroInterpreter::Opcode MacroInterpreter::GetOpcode(u32 offset) const {
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const auto& macro_memory{maxwell3d.GetMacroMemory()};
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ASSERT((pc % sizeof(u32)) == 0);
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ASSERT((pc + offset) < macro_memory.size() * sizeof(u32));
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return {macro_memory[offset + pc / sizeof(u32)]};
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}
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u32 MacroInterpreter::GetALUResult(ALUOperation operation, u32 src_a, u32 src_b) {
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switch (operation) {
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case ALUOperation::Add: {
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const u64 result{static_cast<u64>(src_a) + src_b};
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carry_flag = result > 0xffffffff;
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return static_cast<u32>(result);
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}
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case ALUOperation::AddWithCarry: {
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const u64 result{static_cast<u64>(src_a) + src_b + (carry_flag ? 1ULL : 0ULL)};
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carry_flag = result > 0xffffffff;
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return static_cast<u32>(result);
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}
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case ALUOperation::Subtract: {
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const u64 result{static_cast<u64>(src_a) - src_b};
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carry_flag = result < 0x100000000;
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return static_cast<u32>(result);
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}
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case ALUOperation::SubtractWithBorrow: {
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const u64 result{static_cast<u64>(src_a) - src_b - (carry_flag ? 0ULL : 1ULL)};
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carry_flag = result < 0x100000000;
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return static_cast<u32>(result);
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}
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case ALUOperation::Xor:
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return src_a ^ src_b;
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case ALUOperation::Or:
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return src_a | src_b;
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case ALUOperation::And:
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return src_a & src_b;
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case ALUOperation::AndNot:
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return src_a & ~src_b;
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case ALUOperation::Nand:
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return ~(src_a & src_b);
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default:
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UNIMPLEMENTED_MSG("Unimplemented ALU operation {}", static_cast<u32>(operation));
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return 0;
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}
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}
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void MacroInterpreter::ProcessResult(ResultOperation operation, u32 reg, u32 result) {
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switch (operation) {
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case ResultOperation::IgnoreAndFetch:
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// Fetch parameter and ignore result.
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SetRegister(reg, FetchParameter());
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break;
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case ResultOperation::Move:
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// Move result.
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SetRegister(reg, result);
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break;
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case ResultOperation::MoveAndSetMethod:
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// Move result and use as Method Address.
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SetRegister(reg, result);
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SetMethodAddress(result);
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break;
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case ResultOperation::FetchAndSend:
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// Fetch parameter and send result.
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SetRegister(reg, FetchParameter());
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Send(result);
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break;
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case ResultOperation::MoveAndSend:
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// Move and send result.
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SetRegister(reg, result);
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Send(result);
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break;
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case ResultOperation::FetchAndSetMethod:
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// Fetch parameter and use result as Method Address.
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SetRegister(reg, FetchParameter());
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SetMethodAddress(result);
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break;
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case ResultOperation::MoveAndSetMethodFetchAndSend:
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// Move result and use as Method Address, then fetch and send parameter.
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SetRegister(reg, result);
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SetMethodAddress(result);
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Send(FetchParameter());
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break;
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case ResultOperation::MoveAndSetMethodSend:
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// Move result and use as Method Address, then send bits 12:17 of result.
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SetRegister(reg, result);
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SetMethodAddress(result);
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Send((result >> 12) & 0b111111);
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break;
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default:
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UNIMPLEMENTED_MSG("Unimplemented result operation {}", static_cast<u32>(operation));
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}
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}
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u32 MacroInterpreter::FetchParameter() {
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ASSERT(next_parameter_index < parameters.size());
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return parameters[next_parameter_index++];
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}
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u32 MacroInterpreter::GetRegister(u32 register_id) const {
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return registers.at(register_id);
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}
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void MacroInterpreter::SetRegister(u32 register_id, u32 value) {
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// Register 0 is hardwired as the zero register.
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// Ensure no writes to it actually occur.
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if (register_id == 0) {
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return;
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}
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registers.at(register_id) = value;
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}
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void MacroInterpreter::SetMethodAddress(u32 address) {
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method_address.raw = address;
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}
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void MacroInterpreter::Send(u32 value) {
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maxwell3d.CallMethod({method_address.address, value});
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// Increment the method address by the method increment.
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method_address.address.Assign(method_address.address.Value() +
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method_address.increment.Value());
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}
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u32 MacroInterpreter::Read(u32 method) const {
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return maxwell3d.GetRegisterValue(method);
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}
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bool MacroInterpreter::EvaluateBranchCondition(BranchCondition cond, u32 value) const {
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switch (cond) {
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case BranchCondition::Zero:
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return value == 0;
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case BranchCondition::NotZero:
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return value != 0;
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}
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UNREACHABLE();
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return true;
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}
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} // namespace Tegra
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