c1e5525fc6
These three source files are the only ones within the engines directory that don't use nested namespaces. We may as well change these over to keep things consistent.
121 lines
4.9 KiB
C++
121 lines
4.9 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "core/memory.h"
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra::Engines {
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MaxwellDMA::MaxwellDMA(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager)
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: memory_manager(memory_manager), rasterizer{rasterizer} {}
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void MaxwellDMA::WriteReg(u32 method, u32 value) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid MaxwellDMA register, increase the size of the Regs structure");
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regs.reg_array[method] = value;
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#define MAXWELLDMA_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::MaxwellDMA::Regs, field_name) / sizeof(u32))
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switch (method) {
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case MAXWELLDMA_REG_INDEX(exec): {
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HandleCopy();
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break;
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}
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}
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#undef MAXWELLDMA_REG_INDEX
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}
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void MaxwellDMA::HandleCopy() {
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LOG_WARNING(HW_GPU, "Requested a DMA copy");
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const GPUVAddr source = regs.src_address.Address();
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const GPUVAddr dest = regs.dst_address.Address();
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const VAddr source_cpu = *memory_manager.GpuToCpuAddress(source);
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const VAddr dest_cpu = *memory_manager.GpuToCpuAddress(dest);
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// TODO(Subv): Perform more research and implement all features of this engine.
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ASSERT(regs.exec.enable_swizzle == 0);
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ASSERT(regs.exec.query_mode == Regs::QueryMode::None);
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ASSERT(regs.exec.query_intr == Regs::QueryIntr::None);
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ASSERT(regs.exec.copy_mode == Regs::CopyMode::Unk2);
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ASSERT(regs.dst_params.pos_x == 0);
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ASSERT(regs.dst_params.pos_y == 0);
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if (!regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
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// If both the source and the destination are in block layout, assert.
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UNREACHABLE_MSG("Tiled->Tiled DMA transfers are not yet implemented");
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return;
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}
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if (regs.exec.is_dst_linear && regs.exec.is_src_linear) {
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// When the enable_2d bit is disabled, the copy is performed as if we were copying a 1D
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// buffer of length `x_count`, otherwise we copy a 2D image of dimensions (x_count,
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// y_count).
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if (!regs.exec.enable_2d) {
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Memory::CopyBlock(dest_cpu, source_cpu, regs.x_count);
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return;
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}
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// If both the source and the destination are in linear layout, perform a line-by-line
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// copy. We're going to take a subrect of size (x_count, y_count) from the source
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// rectangle. There is no need to manually flush/invalidate the regions because
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// CopyBlock does that for us.
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for (u32 line = 0; line < regs.y_count; ++line) {
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const VAddr source_line = source_cpu + line * regs.src_pitch;
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const VAddr dest_line = dest_cpu + line * regs.dst_pitch;
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Memory::CopyBlock(dest_line, source_line, regs.x_count);
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}
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return;
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}
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ASSERT(regs.exec.enable_2d == 1);
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const std::size_t copy_size = regs.x_count * regs.y_count;
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const auto FlushAndInvalidate = [&](u32 src_size, u64 dst_size) {
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// TODO(Subv): For now, manually flush the regions until we implement GPU-accelerated
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// copying.
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rasterizer.FlushRegion(source_cpu, src_size);
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// We have to invalidate the destination region to evict any outdated surfaces from the
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// cache. We do this before actually writing the new data because the destination address
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// might contain a dirty surface that will have to be written back to memory.
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rasterizer.InvalidateRegion(dest_cpu, dst_size);
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};
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if (regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
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ASSERT(regs.src_params.size_z == 1);
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// If the input is tiled and the output is linear, deswizzle the input and copy it over.
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const u32 src_bytes_per_pixel = regs.src_pitch / regs.src_params.size_x;
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FlushAndInvalidate(regs.src_pitch * regs.src_params.size_y,
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copy_size * src_bytes_per_pixel);
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Texture::UnswizzleSubrect(regs.x_count, regs.y_count, regs.dst_pitch,
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regs.src_params.size_x, src_bytes_per_pixel, source_cpu, dest_cpu,
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regs.src_params.BlockHeight(), regs.src_params.pos_x,
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regs.src_params.pos_y);
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} else {
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ASSERT(regs.dst_params.size_z == 1);
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ASSERT(regs.src_pitch == regs.x_count);
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const u32 src_bpp = regs.src_pitch / regs.x_count;
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FlushAndInvalidate(regs.src_pitch * regs.y_count,
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regs.dst_params.size_x * regs.dst_params.size_y * src_bpp);
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// If the input is linear and the output is tiled, swizzle the input and copy it over.
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Texture::SwizzleSubrect(regs.x_count, regs.y_count, regs.src_pitch, regs.dst_params.size_x,
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src_bpp, dest_cpu, source_cpu, regs.dst_params.BlockHeight());
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}
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}
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} // namespace Tegra::Engines
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