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Shader_Ir: Change Debug Asserts for Log Warnings

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This commit is contained in:
Fernando Sahmkow 2019-07-19 22:15:34 -04:00
parent 5a06e33859
commit 1158777737
3 changed files with 17 additions and 10 deletions
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11
src/video_core/shader/decode/arithmetic.cpp
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@ -42,11 +42,14 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) {
case OpCode::Id::FMUL_R: case OpCode::Id::FMUL_R:
case OpCode::Id::FMUL_IMM: { case OpCode::Id::FMUL_IMM: {
// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit. // FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
DEBUG_ASSERT_MSG(instr.fmul.tab5cb8_2 == 0, "FMUL tab5cb8_2({}) is not implemented", if (instr.fmul.tab5cb8_2 != 0) {
LOG_WARNING(HW_GPU, "FMUL tab5cb8_2({}) is not implemented",
instr.fmul.tab5cb8_2.Value()); instr.fmul.tab5cb8_2.Value());
DEBUG_ASSERT_MSG( }
instr.fmul.tab5c68_0 == 1, "FMUL tab5cb8_0({}) is not implemented", if (instr.fmul.tab5c68_0 != 1) {
instr.fmul.tab5c68_0.Value()); // SMO typical sends 1 here which seems to be the default LOG_WARNING(HW_GPU, "FMUL tab5cb8_0({}) is not implemented",
instr.fmul.tab5c68_0.Value());
}
op_b = GetOperandAbsNegFloat(op_b, false, instr.fmul.negate_b); op_b = GetOperandAbsNegFloat(op_b, false, instr.fmul.negate_b);

4
src/video_core/shader/decode/arithmetic_half_immediate.cpp
View file

@ -23,7 +23,9 @@ u32 ShaderIR::DecodeArithmeticHalfImmediate(NodeBlock& bb, u32 pc) {
LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName()); LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName());
} }
} else { } else {
DEBUG_ASSERT(instr.alu_half_imm.precision == Tegra::Shader::HalfPrecision::None); if (instr.alu_half_imm.precision != Tegra::Shader::HalfPrecision::None) {
LOG_WARNING(HW_GPU, "{} FTZ not implemented", opcode->get().GetName());
}
} }
Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.alu_half_imm.type_a); Node op_a = UnpackHalfFloat(GetRegister(instr.gpr8), instr.alu_half_imm.type_a);

10
src/video_core/shader/decode/ffma.cpp
View file

@ -18,10 +18,12 @@ u32 ShaderIR::DecodeFfma(NodeBlock& bb, u32 pc) {
const auto opcode = OpCode::Decode(instr); const auto opcode = OpCode::Decode(instr);
UNIMPLEMENTED_IF_MSG(instr.ffma.cc != 0, "FFMA cc not implemented"); UNIMPLEMENTED_IF_MSG(instr.ffma.cc != 0, "FFMA cc not implemented");
DEBUG_ASSERT_MSG(instr.ffma.tab5980_0 == 1, "FFMA tab5980_0({}) not implemented", if (instr.ffma.tab5980_0 != 1) {
instr.ffma.tab5980_0.Value()); // Seems to be 1 by default based on SMO LOG_WARNING(HW_GPU, "FFMA tab5980_0({}) not implemented", instr.ffma.tab5980_0.Value());
DEBUG_ASSERT_MSG(instr.ffma.tab5980_1 == 0, "FFMA tab5980_1({}) not implemented", }
instr.ffma.tab5980_1.Value()); if (instr.ffma.tab5980_1 != 0) {
LOG_WARNING(HW_GPU, "FFMA tab5980_1({}) not implemented", instr.ffma.tab5980_1.Value());
}
const Node op_a = GetRegister(instr.gpr8); const Node op_a = GetRegister(instr.gpr8);