2018-12-20 23:09:21 +01:00
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeBfi(BasicBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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2018-12-17 21:09:23 +01:00
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UNIMPLEMENTED_IF(instr.generates_cc);
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const auto [base, packed_shift] = [&]() -> std::tuple<Node, Node> {
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switch (opcode->get().GetId()) {
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case OpCode::Id::BFI_IMM_R:
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return {GetRegister(instr.gpr39), Immediate(instr.alu.GetSignedImm20_20())};
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default:
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UNREACHABLE();
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}
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}();
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const Node insert = GetRegister(instr.gpr8);
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const Node offset =
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Operation(OperationCode::UBitwiseAnd, NO_PRECISE, packed_shift, Immediate(0xff));
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Node bits =
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Operation(OperationCode::ULogicalShiftRight, NO_PRECISE, packed_shift, Immediate(8));
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bits = Operation(OperationCode::UBitwiseAnd, NO_PRECISE, bits, Immediate(0xff));
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const Node value =
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Operation(OperationCode::UBitfieldInsert, PRECISE, base, insert, offset, bits);
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SetRegister(bb, instr.gpr0, value);
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2018-12-20 23:09:21 +01:00
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return pc;
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}
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} // namespace VideoCommon::Shader
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