shader_ir: Add comments on missing instruction.
Also shows Nvidia's address space on comments.
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2de7649311
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f2549739d1
2 changed files with 9 additions and 2 deletions
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@ -146,15 +146,18 @@ u32 ShaderIR::DecodeInstr(NodeBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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const auto opcode = OpCode::Decode(instr);
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const u32 nv_address = ConvertAddressToNvidiaSpace(pc);
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// Decoding failure
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// Decoding failure
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if (!opcode) {
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if (!opcode) {
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UNIMPLEMENTED_MSG("Unhandled instruction: {0:x}", instr.value);
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UNIMPLEMENTED_MSG("Unhandled instruction: {0:x}", instr.value);
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bb.push_back(Comment(fmt::format("{:05x} Unimplemented Shader instruction (0x{:016x})",
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nv_address, instr.value)));
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return pc + 1;
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return pc + 1;
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}
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}
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bb.push_back(
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bb.push_back(Comment(
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Comment(fmt::format("{}: {} (0x{:016x})", pc, opcode->get().GetName(), instr.value)));
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fmt::format("{:05x} {} (0x{:016x})", nv_address, opcode->get().GetName(), instr.value)));
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using Tegra::Shader::Pred;
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using Tegra::Shader::Pred;
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UNIMPLEMENTED_IF_MSG(instr.pred.full_pred == Pred::NeverExecute,
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UNIMPLEMENTED_IF_MSG(instr.pred.full_pred == Pred::NeverExecute,
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@ -127,6 +127,10 @@ public:
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return disable_flow_stack;
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return disable_flow_stack;
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}
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}
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u32 ConvertAddressToNvidiaSpace(const u32 address) const {
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return (address - main_offset) * sizeof(Tegra::Shader::Instruction);
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}
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private:
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private:
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void Decode();
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void Decode();
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