vk_graphics_pipeline: Manage primitive topology as fixed state
Vulkan has requirements for primitive topologies that don't play nicely with yuzu's. Since it's only 4 bits, we can move it to fixed state without changing the size of the pipeline key. - Fixes a regression on recent Nvidia drivers on Fire Emblem: Three Houses.
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4c348f4069
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e4e0abc418
6 changed files with 7 additions and 26 deletions
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@ -58,6 +58,7 @@ void FixedPipelineState::Fill(const Maxwell& regs, bool has_extended_dynamic_sta
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logic_op_enable.Assign(regs.logic_op.enable != 0 ? 1 : 0);
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logic_op_enable.Assign(regs.logic_op.enable != 0 ? 1 : 0);
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logic_op.Assign(PackLogicOp(regs.logic_op.operation));
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logic_op.Assign(PackLogicOp(regs.logic_op.operation));
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rasterize_enable.Assign(regs.rasterize_enable != 0 ? 1 : 0);
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rasterize_enable.Assign(regs.rasterize_enable != 0 ? 1 : 0);
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topology.Assign(regs.draw.topology);
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std::memcpy(&point_size, ®s.point_size, sizeof(point_size)); // TODO: C++20 std::bit_cast
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std::memcpy(&point_size, ®s.point_size, sizeof(point_size)); // TODO: C++20 std::bit_cast
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@ -131,7 +132,6 @@ void FixedPipelineState::BlendingAttachment::Fill(const Maxwell& regs, std::size
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}
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}
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void FixedPipelineState::DynamicState::Fill(const Maxwell& regs) {
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void FixedPipelineState::DynamicState::Fill(const Maxwell& regs) {
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const u32 topology_index = static_cast<u32>(regs.draw.topology.Value());
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u32 packed_front_face = PackFrontFace(regs.front_face);
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u32 packed_front_face = PackFrontFace(regs.front_face);
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if (regs.screen_y_control.triangle_rast_flip != 0) {
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if (regs.screen_y_control.triangle_rast_flip != 0) {
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// Flip front face
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// Flip front face
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@ -161,7 +161,6 @@ void FixedPipelineState::DynamicState::Fill(const Maxwell& regs) {
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depth_test_enable.Assign(regs.depth_test_enable);
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depth_test_enable.Assign(regs.depth_test_enable);
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front_face.Assign(packed_front_face);
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front_face.Assign(packed_front_face);
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depth_test_func.Assign(PackComparisonOp(regs.depth_test_func));
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depth_test_func.Assign(PackComparisonOp(regs.depth_test_func));
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topology.Assign(topology_index);
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cull_face.Assign(PackCullFace(regs.cull_face));
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cull_face.Assign(PackCullFace(regs.cull_face));
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cull_enable.Assign(regs.cull_test_enabled != 0 ? 1 : 0);
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cull_enable.Assign(regs.cull_test_enabled != 0 ? 1 : 0);
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@ -150,9 +150,8 @@ struct FixedPipelineState {
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};
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};
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union {
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union {
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u32 raw2;
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u32 raw2;
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BitField<0, 4, u32> topology;
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BitField<0, 2, u32> cull_face;
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BitField<4, 2, u32> cull_face;
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BitField<2, 1, u32> cull_enable;
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BitField<6, 1, u32> cull_enable;
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};
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};
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std::array<VertexBinding, Maxwell::NumVertexArrays> vertex_bindings;
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std::array<VertexBinding, Maxwell::NumVertexArrays> vertex_bindings;
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@ -169,10 +168,6 @@ struct FixedPipelineState {
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Maxwell::FrontFace FrontFace() const noexcept {
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Maxwell::FrontFace FrontFace() const noexcept {
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return UnpackFrontFace(front_face.Value());
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return UnpackFrontFace(front_face.Value());
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}
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}
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constexpr Maxwell::PrimitiveTopology Topology() const noexcept {
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return static_cast<Maxwell::PrimitiveTopology>(topology.Value());
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}
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};
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};
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union {
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union {
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@ -190,6 +185,7 @@ struct FixedPipelineState {
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BitField<18, 1, u32> logic_op_enable;
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BitField<18, 1, u32> logic_op_enable;
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BitField<19, 4, u32> logic_op;
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BitField<19, 4, u32> logic_op;
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BitField<23, 1, u32> rasterize_enable;
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BitField<23, 1, u32> rasterize_enable;
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BitField<24, 4, Maxwell::PrimitiveTopology> topology;
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};
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};
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u32 point_size;
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u32 point_size;
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std::array<u32, Maxwell::NumVertexArrays> binding_divisors;
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std::array<u32, Maxwell::NumVertexArrays> binding_divisors;
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@ -261,12 +261,12 @@ vk::Pipeline VKGraphicsPipeline::CreatePipeline(const RenderPassParams& renderpa
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vertex_input_ci.pNext = &input_divisor_ci;
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vertex_input_ci.pNext = &input_divisor_ci;
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}
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}
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const auto input_assembly_topology = MaxwellToVK::PrimitiveTopology(device, dynamic.Topology());
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const auto input_assembly_topology = MaxwellToVK::PrimitiveTopology(device, state.topology);
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const VkPipelineInputAssemblyStateCreateInfo input_assembly_ci{
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const VkPipelineInputAssemblyStateCreateInfo input_assembly_ci{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
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.sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
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.pNext = nullptr,
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.pNext = nullptr,
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.flags = 0,
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.flags = 0,
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.topology = MaxwellToVK::PrimitiveTopology(device, dynamic.Topology()),
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.topology = MaxwellToVK::PrimitiveTopology(device, state.topology),
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.primitiveRestartEnable = state.primitive_restart_enable != 0 &&
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.primitiveRestartEnable = state.primitive_restart_enable != 0 &&
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SupportsPrimitiveRestart(input_assembly_topology),
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SupportsPrimitiveRestart(input_assembly_topology),
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};
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};
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@ -400,7 +400,6 @@ vk::Pipeline VKGraphicsPipeline::CreatePipeline(const RenderPassParams& renderpa
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static constexpr std::array extended{
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static constexpr std::array extended{
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VK_DYNAMIC_STATE_CULL_MODE_EXT,
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VK_DYNAMIC_STATE_CULL_MODE_EXT,
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VK_DYNAMIC_STATE_FRONT_FACE_EXT,
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VK_DYNAMIC_STATE_FRONT_FACE_EXT,
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VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT,
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VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT,
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VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT,
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VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT,
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VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT,
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VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
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VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
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@ -331,8 +331,7 @@ void VKPipelineCache::OnShaderRemoval(Shader* shader) {
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std::pair<SPIRVProgram, std::vector<VkDescriptorSetLayoutBinding>>
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std::pair<SPIRVProgram, std::vector<VkDescriptorSetLayoutBinding>>
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VKPipelineCache::DecompileShaders(const FixedPipelineState& fixed_state) {
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VKPipelineCache::DecompileShaders(const FixedPipelineState& fixed_state) {
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Specialization specialization;
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Specialization specialization;
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if (fixed_state.dynamic_state.Topology() == Maxwell::PrimitiveTopology::Points ||
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if (fixed_state.topology == Maxwell::PrimitiveTopology::Points) {
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device.IsExtExtendedDynamicStateSupported()) {
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float point_size;
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float point_size;
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std::memcpy(&point_size, &fixed_state.point_size, sizeof(float));
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std::memcpy(&point_size, &fixed_state.point_size, sizeof(float));
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specialization.point_size = point_size;
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specialization.point_size = point_size;
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@ -948,7 +948,6 @@ void RasterizerVulkan::UpdateDynamicStates() {
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UpdateDepthWriteEnable(regs);
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UpdateDepthWriteEnable(regs);
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UpdateDepthCompareOp(regs);
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UpdateDepthCompareOp(regs);
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UpdateFrontFace(regs);
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UpdateFrontFace(regs);
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UpdatePrimitiveTopology(regs);
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UpdateStencilOp(regs);
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UpdateStencilOp(regs);
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UpdateStencilTestEnable(regs);
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UpdateStencilTestEnable(regs);
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}
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}
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@ -1418,16 +1417,6 @@ void RasterizerVulkan::UpdateFrontFace(Tegra::Engines::Maxwell3D::Regs& regs) {
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[front_face](vk::CommandBuffer cmdbuf) { cmdbuf.SetFrontFaceEXT(front_face); });
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[front_face](vk::CommandBuffer cmdbuf) { cmdbuf.SetFrontFaceEXT(front_face); });
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}
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}
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void RasterizerVulkan::UpdatePrimitiveTopology(Tegra::Engines::Maxwell3D::Regs& regs) {
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const Maxwell::PrimitiveTopology primitive_topology = regs.draw.topology.Value();
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if (!state_tracker.ChangePrimitiveTopology(primitive_topology)) {
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return;
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}
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scheduler.Record([this, primitive_topology](vk::CommandBuffer cmdbuf) {
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cmdbuf.SetPrimitiveTopologyEXT(MaxwellToVK::PrimitiveTopology(device, primitive_topology));
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});
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}
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void RasterizerVulkan::UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs) {
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void RasterizerVulkan::UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs) {
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if (!state_tracker.TouchStencilOp()) {
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if (!state_tracker.TouchStencilOp()) {
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return;
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return;
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@ -259,7 +259,6 @@ private:
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void UpdateDepthWriteEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateDepthWriteEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateDepthCompareOp(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateDepthCompareOp(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateFrontFace(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateFrontFace(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdatePrimitiveTopology(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateStencilTestEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateStencilTestEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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