mctaylors/suyu
1
0
Fork 0
forked from suyu/suyu
Code Pull requests Activity

armemu: Simplify REVSH/UXTH/UXTAH

Browse source
This commit is contained in:
Lioncash 2014-12-28 11:45:13 -05:00
parent 3422d81f05
commit 5e16216afb
1 changed files with 23 additions and 48 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

53
src/core/arm/interpreter/armemu.cpp
View file

@ -6496,59 +6496,34 @@ L_stm_s_takeabort:
return 1;
}
case 0x6f: {
ARMword Rm;
int ror = -1;
switch (BITS(4, 11)) {
case 0x07:
ror = 0;
break;
case 0x47:
ror = 8;
break;
case 0x87:
ror = 16;
break;
case 0xc7:
ror = 24;
break;
case 0xfb: // REVSH
case 0x6f: // UXTH, UXTAH, and REVSH.
{
const u8 op2 = BITS(5, 7);
// REVSH
if (op2 == 0x05) {
DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00) >> 8);
if (DEST & 0x8000)
DEST |= 0xffff0000;
return 1;
}
default:
break;
}
// UXTH and UXTAH
else if (op2 == 0x03) {
const u8 rotate = BITS(10, 11) * 8;
const ARMword rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFFFF) & 0xFFFF);
if (ror == -1)
break;
Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF);
/* UXT */
/* state->Reg[BITS (12, 15)] = Rm; */
/* dyf add */
// UXTH
if (BITS(16, 19) == 0xf) {
state->Reg[BITS(12, 15)] = Rm;
state->Reg[BITS(12, 15)] = rm;
}
// UXTAH
else {
/* UXTAH */
/* state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm; */
// printf("rd is %x rn is %x rm is %x rotate is %x\n", state->Reg[BITS (12, 15)], state->Reg[BITS (16, 19)]
// , Rm, BITS(10, 11));
// printf("icounter is %lld\n", state->NumInstrs);
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
// printf("rd is %x\n", state->Reg[BITS (12, 15)]);
// exit(-1);
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm;
}
return 1;
}
}
case 0x70:
// ichfly
// SMUAD, SMUSD, SMLAD, and SMLSD