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core: arm: Remove unnecessary JIT checks.

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This commit is contained in:
bunnei 2021-01-24 22:51:12 -08:00
parent 091e9e8c41
commit 055194d2ab
2 changed files with 0 additions and 24 deletions
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12
src/core/arm/dynarmic/arm_dynarmic_32.cpp
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@ -251,16 +251,10 @@ void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
} }
void ARM_Dynarmic_32::ChangeProcessorID(std::size_t new_core_id) { void ARM_Dynarmic_32::ChangeProcessorID(std::size_t new_core_id) {
if (!jit) {
return;
}
jit->ChangeProcessorID(new_core_id); jit->ChangeProcessorID(new_core_id);
} }
void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) { void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
if (!jit) {
return;
}
Dynarmic::A32::Context context; Dynarmic::A32::Context context;
jit->SaveContext(context); jit->SaveContext(context);
ctx.cpu_registers = context.Regs(); ctx.cpu_registers = context.Regs();
@ -270,9 +264,6 @@ void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
} }
void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
if (!jit) {
return;
}
Dynarmic::A32::Context context; Dynarmic::A32::Context context;
context.Regs() = ctx.cpu_registers; context.Regs() = ctx.cpu_registers;
context.ExtRegs() = ctx.extension_registers; context.ExtRegs() = ctx.extension_registers;
@ -282,9 +273,6 @@ void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
} }
void ARM_Dynarmic_32::PrepareReschedule() { void ARM_Dynarmic_32::PrepareReschedule() {
if (!jit) {
return;
}
jit->HaltExecution(); jit->HaltExecution();
} }

12
src/core/arm/dynarmic/arm_dynarmic_64.cpp
View file

@ -290,16 +290,10 @@ void ARM_Dynarmic_64::SetTPIDR_EL0(u64 value) {
} }
void ARM_Dynarmic_64::ChangeProcessorID(std::size_t new_core_id) { void ARM_Dynarmic_64::ChangeProcessorID(std::size_t new_core_id) {
if (!jit) {
return;
}
jit->ChangeProcessorID(new_core_id); jit->ChangeProcessorID(new_core_id);
} }
void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) { void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) {
if (!jit) {
return;
}
ctx.cpu_registers = jit->GetRegisters(); ctx.cpu_registers = jit->GetRegisters();
ctx.sp = jit->GetSP(); ctx.sp = jit->GetSP();
ctx.pc = jit->GetPC(); ctx.pc = jit->GetPC();
@ -311,9 +305,6 @@ void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) {
} }
void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) { void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
if (!jit) {
return;
}
jit->SetRegisters(ctx.cpu_registers); jit->SetRegisters(ctx.cpu_registers);
jit->SetSP(ctx.sp); jit->SetSP(ctx.sp);
jit->SetPC(ctx.pc); jit->SetPC(ctx.pc);
@ -325,9 +316,6 @@ void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
} }
void ARM_Dynarmic_64::PrepareReschedule() { void ARM_Dynarmic_64::PrepareReschedule() {
if (!jit) {
return;
}
jit->HaltExecution(); jit->HaltExecution();
} }