267 lines
7.5 KiB
C++
267 lines
7.5 KiB
C++
// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include <memory>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "core/hle/service/nvdrv/nvdata.h"
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#include "video_core/cdma_pusher.h"
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#include "video_core/framebuffer_config.h"
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#include "video_core/rasterizer_download_area.h"
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namespace Core {
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class System;
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} // namespace Core
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namespace VideoCore {
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class RendererBase;
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class ShaderNotify;
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} // namespace VideoCore
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namespace Tegra {
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class DmaPusher;
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struct CommandList;
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// TODO: Implement the commented ones
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enum class RenderTargetFormat : u32 {
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NONE = 0x0,
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R32G32B32A32_FLOAT = 0xC0,
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R32G32B32A32_SINT = 0xC1,
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R32G32B32A32_UINT = 0xC2,
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R32G32B32X32_FLOAT = 0xC3,
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R32G32B32X32_SINT = 0xC4,
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R32G32B32X32_UINT = 0xC5,
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R16G16B16A16_UNORM = 0xC6,
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R16G16B16A16_SNORM = 0xC7,
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R16G16B16A16_SINT = 0xC8,
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R16G16B16A16_UINT = 0xC9,
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R16G16B16A16_FLOAT = 0xCA,
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R32G32_FLOAT = 0xCB,
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R32G32_SINT = 0xCC,
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R32G32_UINT = 0xCD,
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R16G16B16X16_FLOAT = 0xCE,
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A8R8G8B8_UNORM = 0xCF,
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A8R8G8B8_SRGB = 0xD0,
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A2B10G10R10_UNORM = 0xD1,
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A2B10G10R10_UINT = 0xD2,
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A8B8G8R8_UNORM = 0xD5,
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A8B8G8R8_SRGB = 0xD6,
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A8B8G8R8_SNORM = 0xD7,
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A8B8G8R8_SINT = 0xD8,
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A8B8G8R8_UINT = 0xD9,
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R16G16_UNORM = 0xDA,
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R16G16_SNORM = 0xDB,
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R16G16_SINT = 0xDC,
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R16G16_UINT = 0xDD,
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R16G16_FLOAT = 0xDE,
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A2R10G10B10_UNORM = 0xDF,
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B10G11R11_FLOAT = 0xE0,
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R32_SINT = 0xE3,
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R32_UINT = 0xE4,
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R32_FLOAT = 0xE5,
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X8R8G8B8_UNORM = 0xE6,
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X8R8G8B8_SRGB = 0xE7,
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R5G6B5_UNORM = 0xE8,
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A1R5G5B5_UNORM = 0xE9,
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R8G8_UNORM = 0xEA,
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R8G8_SNORM = 0xEB,
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R8G8_SINT = 0xEC,
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R8G8_UINT = 0xED,
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R16_UNORM = 0xEE,
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R16_SNORM = 0xEF,
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R16_SINT = 0xF0,
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R16_UINT = 0xF1,
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R16_FLOAT = 0xF2,
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R8_UNORM = 0xF3,
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R8_SNORM = 0xF4,
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R8_SINT = 0xF5,
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R8_UINT = 0xF6,
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// A8_UNORM = 0xF7,
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X1R5G5B5_UNORM = 0xF8,
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X8B8G8R8_UNORM = 0xF9,
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X8B8G8R8_SRGB = 0xFA,
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/*
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Z1R5G5B5_UNORM = 0xFB,
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O1R5G5B5_UNORM = 0xFC,
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Z8R8G8B8_UNORM = 0xFD,
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O8R8G8B8_UNORM = 0xFE,
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R32_UNORM = 0xFF,
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A16_UNORM = 0x40,
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A16_FLOAT = 0x41,
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A32_FLOAT = 0x42,
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A8R8_UNORM = 0x43,
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R16A16_UNORM = 0x44,
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R16A16_FLOAT = 0x45,
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R32A32_FLOAT = 0x46,
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B8G8R8A8_UNORM = 0x47,
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*/
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};
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enum class DepthFormat : u32 {
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Z32_FLOAT = 0xA,
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Z16_UNORM = 0x13,
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Z24_UNORM_S8_UINT = 0x14,
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X8Z24_UNORM = 0x15,
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S8Z24_UNORM = 0x16,
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S8_UINT = 0x17,
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V8Z24_UNORM = 0x18,
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Z32_FLOAT_X24S8_UINT = 0x19,
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/*
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X8Z24_UNORM_X16V8S8_UINT = 0x1D,
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Z32_FLOAT_X16V8X8_UINT = 0x1E,
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Z32_FLOAT_X16V8S8_UINT = 0x1F,
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*/
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};
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namespace Engines {
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class Maxwell3D;
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class KeplerCompute;
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} // namespace Engines
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namespace Control {
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struct ChannelState;
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}
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namespace Host1x {
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class Host1x;
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} // namespace Host1x
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class MemoryManager;
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class GPU final {
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public:
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explicit GPU(Core::System& system, bool is_async, bool use_nvdec);
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~GPU();
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/// Binds a renderer to the GPU.
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void BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer);
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/// Flush all current written commands into the host GPU for execution.
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void FlushCommands();
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/// Synchronizes CPU writes with Host GPU memory.
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void InvalidateGPUCache();
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/// Signal the ending of command list.
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void OnCommandListEnd();
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std::shared_ptr<Control::ChannelState> AllocateChannel();
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void InitChannel(Control::ChannelState& to_init, u64 program_id);
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void BindChannel(s32 channel_id);
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void ReleaseChannel(Control::ChannelState& to_release);
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void InitAddressSpace(Tegra::MemoryManager& memory_manager);
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/// Request a host GPU memory flush from the CPU.
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[[nodiscard]] u64 RequestFlush(DAddr addr, std::size_t size);
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/// Obtains current flush request fence id.
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[[nodiscard]] u64 CurrentSyncRequestFence() const;
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void WaitForSyncOperation(u64 fence);
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/// Tick pending requests within the GPU.
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void TickWork();
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/// Gets a mutable reference to the Host1x interface
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[[nodiscard]] Host1x::Host1x& Host1x();
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/// Gets an immutable reference to the Host1x interface.
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[[nodiscard]] const Host1x::Host1x& Host1x() const;
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/// Returns a reference to the Maxwell3D GPU engine.
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[[nodiscard]] Engines::Maxwell3D& Maxwell3D();
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/// Returns a const reference to the Maxwell3D GPU engine.
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[[nodiscard]] const Engines::Maxwell3D& Maxwell3D() const;
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/// Returns a reference to the KeplerCompute GPU engine.
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[[nodiscard]] Engines::KeplerCompute& KeplerCompute();
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/// Returns a reference to the KeplerCompute GPU engine.
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[[nodiscard]] const Engines::KeplerCompute& KeplerCompute() const;
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/// Returns a reference to the GPU DMA pusher.
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[[nodiscard]] Tegra::DmaPusher& DmaPusher();
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/// Returns a const reference to the GPU DMA pusher.
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[[nodiscard]] const Tegra::DmaPusher& DmaPusher() const;
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/// Returns a reference to the underlying renderer.
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[[nodiscard]] VideoCore::RendererBase& Renderer();
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/// Returns a const reference to the underlying renderer.
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[[nodiscard]] const VideoCore::RendererBase& Renderer() const;
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/// Returns a reference to the shader notifier.
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[[nodiscard]] VideoCore::ShaderNotify& ShaderNotify();
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/// Returns a const reference to the shader notifier.
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[[nodiscard]] const VideoCore::ShaderNotify& ShaderNotify() const;
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[[nodiscard]] u64 GetTicks() const;
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[[nodiscard]] bool IsAsync() const;
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[[nodiscard]] bool UseNvdec() const;
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void RendererFrameEndNotify();
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void RequestComposite(std::vector<Tegra::FramebufferConfig>&& layers,
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std::vector<Service::Nvidia::NvFence>&& fences);
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std::vector<u8> GetAppletCaptureBuffer();
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/// Performs any additional setup necessary in order to begin GPU emulation.
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/// This can be used to launch any necessary threads and register any necessary
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/// core timing events.
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void Start();
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/// Performs any additional necessary steps to shutdown GPU emulation.
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void NotifyShutdown();
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/// Obtain the CPU Context
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void ObtainContext();
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/// Release the CPU Context
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void ReleaseContext();
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/// Push GPU command entries to be processed
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void PushGPUEntries(s32 channel, Tegra::CommandList&& entries);
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/// Push GPU command buffer entries to be processed
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void PushCommandBuffer(u32 id, Tegra::ChCommandHeaderList& entries);
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/// Frees the CDMAPusher instance to free up resources
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void ClearCdmaInstance(u32 id);
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/// Swap buffers (render frame)
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void SwapBuffers(const Tegra::FramebufferConfig* framebuffer);
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/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
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[[nodiscard]] VideoCore::RasterizerDownloadArea OnCPURead(DAddr addr, u64 size);
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/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
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void FlushRegion(DAddr addr, u64 size);
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/// Notify rasterizer that any caches of the specified region should be invalidated
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void InvalidateRegion(DAddr addr, u64 size);
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/// Notify rasterizer that CPU is trying to write this area. It returns true if the area is
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/// sensible, false otherwise
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bool OnCPUWrite(DAddr addr, u64 size);
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/// Notify rasterizer that any caches of the specified region should be flushed and invalidated
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void FlushAndInvalidateRegion(DAddr addr, u64 size);
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private:
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struct Impl;
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mutable std::unique_ptr<Impl> impl;
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};
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} // namespace Tegra
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