lvella/suyu
1
0
Fork 0
forked from suyu/suyu
Code Pull requests Activity

GPU: Added registers for the number of vertices to render.

Browse source
This commit is contained in:
Subv 2018-03-20 23:28:06 -05:00
parent 0b3ab30762
commit ae28a52277
1 changed files with 13 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
src/video_core/engines/maxwell_3d.h
View file

@ -83,7 +83,14 @@ public:
} }
} rt[NumRenderTargets]; } rt[NumRenderTargets];
INSERT_PADDING_WORDS(0x178); INSERT_PADDING_WORDS(0xDD);
struct {
u32 first;
u32 count;
} vertex_buffer;
INSERT_PADDING_WORDS(0x99);
struct { struct {
u32 address_high; u32 address_high;
@ -146,7 +153,10 @@ public:
INSERT_PADDING_WORDS(1); INSERT_PADDING_WORDS(1);
struct { struct {
u32 vertex_end_gl; u32 vertex_end_gl;
union {
u32 vertex_begin_gl; u32 vertex_begin_gl;
BitField<0, 16, u32> topology;
};
} draw; } draw;
INSERT_PADDING_WORDS(0x139); INSERT_PADDING_WORDS(0x139);
struct { struct {
@ -336,6 +346,7 @@ private:
"Field " #field_name " has invalid position") "Field " #field_name " has invalid position")
ASSERT_REG_POSITION(rt, 0x200); ASSERT_REG_POSITION(rt, 0x200);
ASSERT_REG_POSITION(vertex_buffer, 0x35D);
ASSERT_REG_POSITION(zeta, 0x3F8); ASSERT_REG_POSITION(zeta, 0x3F8);
ASSERT_REG_POSITION(rt_control, 0x487); ASSERT_REG_POSITION(rt_control, 0x487);
ASSERT_REG_POSITION(tsc, 0x557); ASSERT_REG_POSITION(tsc, 0x557);