From 5e639bfcf6d764714cc9814fc47142ca85f889cf Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Thu, 20 Dec 2018 22:41:31 -0300
Subject: [PATCH] shader_ir: Add register getter

---
 src/video_core/shader/shader_ir.cpp | 7 +++++++
 src/video_core/shader/shader_ir.h   | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/src/video_core/shader/shader_ir.cpp b/src/video_core/shader/shader_ir.cpp
index c59ecf4573..ff4e462f26 100644
--- a/src/video_core/shader/shader_ir.cpp
+++ b/src/video_core/shader/shader_ir.cpp
@@ -39,6 +39,13 @@ Node ShaderIR::Immediate(u32 value) {
     return StoreNode(ImmediateNode(value));
 }
 
+Node ShaderIR::GetRegister(Register reg) {
+    if (reg != Register::ZeroIndex) {
+        used_registers.insert(static_cast<u32>(reg));
+    }
+    return StoreNode(GprNode(reg));
+}
+
 Node ShaderIR::GetImmediate19(Instruction instr) {
     return Immediate(instr.alu.GetImm20_19());
 }
diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h
index db06d51cac..30b75c3ed2 100644
--- a/src/video_core/shader/shader_ir.h
+++ b/src/video_core/shader/shader_ir.h
@@ -610,6 +610,8 @@ private:
         return Immediate(*reinterpret_cast<const u32*>(&value));
     }
 
+    /// Generates a node for a passed register.
+    Node GetRegister(Tegra::Shader::Register reg);
     /// Generates a node representing a 19-bit immediate value
     Node GetImmediate19(Tegra::Shader::Instruction instr);
     /// Generates a node representing a 32-bit immediate value