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maxwell3d: full HLE for multi-layer clears

This commit is contained in:
Liam 2022-11-16 22:41:40 -05:00
parent ece0c1095d
commit 4c42655a2d
8 changed files with 17 additions and 24 deletions

View file

@ -232,7 +232,7 @@ void Maxwell3D::ProcessMethodCall(u32 method, u32 argument, u32 nonshadow_argume
use_topology_override = true; use_topology_override = true;
return; return;
case MAXWELL3D_REG_INDEX(clear_surface): case MAXWELL3D_REG_INDEX(clear_surface):
return ProcessClearBuffers(); return ProcessClearBuffers(1);
case MAXWELL3D_REG_INDEX(report_semaphore.query): case MAXWELL3D_REG_INDEX(report_semaphore.query):
return ProcessQueryGet(); return ProcessQueryGet();
case MAXWELL3D_REG_INDEX(render_enable.mode): case MAXWELL3D_REG_INDEX(render_enable.mode):
@ -596,8 +596,8 @@ u32 Maxwell3D::GetRegisterValue(u32 method) const {
return regs.reg_array[method]; return regs.reg_array[method];
} }
void Maxwell3D::ProcessClearBuffers() { void Maxwell3D::ProcessClearBuffers(u32 layer_count) {
rasterizer->Clear(); rasterizer->Clear(layer_count);
} }
void Maxwell3D::ProcessDraw(u32 instance_count) { void Maxwell3D::ProcessDraw(u32 instance_count) {

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@ -1129,7 +1129,6 @@ public:
Tegra::RenderTargetFormat format; Tegra::RenderTargetFormat format;
TileMode tile_mode; TileMode tile_mode;
union { union {
u32 depth_volume;
BitField<0, 16, u32> depth; BitField<0, 16, u32> depth;
BitField<16, 1, u32> volume; BitField<16, 1, u32> volume;
}; };
@ -3087,6 +3086,9 @@ public:
std::vector<u8> inline_index_draw_indexes; std::vector<u8> inline_index_draw_indexes;
/// Handles a write to the CLEAR_BUFFERS register.
void ProcessClearBuffers(u32 layer_count);
private: private:
void InitializeRegisterDefaults(); void InitializeRegisterDefaults();
@ -3121,9 +3123,6 @@ private:
/// Handles firmware blob 4 /// Handles firmware blob 4
void ProcessFirmwareCall4(); void ProcessFirmwareCall4();
/// Handles a write to the CLEAR_BUFFERS register.
void ProcessClearBuffers();
/// Handles a write to the QUERY_GET register. /// Handles a write to the QUERY_GET register.
void ProcessQueryGet(); void ProcessQueryGet();

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@ -130,19 +130,13 @@ void HLE_3F5E74B9C9A50164(Engines::Maxwell3D& maxwell3d, const std::vector<u32>&
void HLE_EAD26C3E2109B06B(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) { void HLE_EAD26C3E2109B06B(Engines::Maxwell3D& maxwell3d, const std::vector<u32>& parameters) {
ASSERT(parameters.size() == 1); ASSERT(parameters.size() == 1);
Engines::Maxwell3D::Regs::ClearSurface clear_params{parameters[0]}; const Engines::Maxwell3D::Regs::ClearSurface clear_params{parameters[0]};
const u32 rt_index = clear_params.RT; const u32 rt_index = clear_params.RT;
const u32 num_layers = maxwell3d.regs.rt[rt_index].depth_volume; const u32 num_layers = maxwell3d.regs.rt[rt_index].depth;
ASSERT(clear_params.layer == 0);
for (u32 i = 0; i < num_layers; i++) { maxwell3d.regs.clear_surface.raw = clear_params.raw;
// 0x674 = regs.clear_surface maxwell3d.ProcessClearBuffers(num_layers);
maxwell3d.CallMethod(0x674, clear_params.raw, true);
clear_params.layer.Assign(clear_params.layer + 1);
// FIXME: remove this when amdvlk can clear multiple layers without crashing
break;
}
} }
constexpr std::array<std::pair<u64, HLEFunction>, 5> hle_funcs{{ constexpr std::array<std::pair<u64, HLEFunction>, 5> hle_funcs{{

View file

@ -43,7 +43,7 @@ public:
virtual void Draw(bool is_indexed, u32 instance_count) = 0; virtual void Draw(bool is_indexed, u32 instance_count) = 0;
/// Clear the current framebuffer /// Clear the current framebuffer
virtual void Clear() = 0; virtual void Clear(u32 layer_count) = 0;
/// Dispatches a compute shader invocation /// Dispatches a compute shader invocation
virtual void DispatchCompute() = 0; virtual void DispatchCompute() = 0;

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@ -136,7 +136,7 @@ void RasterizerOpenGL::LoadDiskResources(u64 title_id, std::stop_token stop_load
shader_cache.LoadDiskResources(title_id, stop_loading, callback); shader_cache.LoadDiskResources(title_id, stop_loading, callback);
} }
void RasterizerOpenGL::Clear() { void RasterizerOpenGL::Clear(u32 layer_count) {
MICROPROFILE_SCOPE(OpenGL_Clears); MICROPROFILE_SCOPE(OpenGL_Clears);
if (!maxwell3d->ShouldExecute()) { if (!maxwell3d->ShouldExecute()) {
return; return;

View file

@ -69,7 +69,7 @@ public:
~RasterizerOpenGL() override; ~RasterizerOpenGL() override;
void Draw(bool is_indexed, u32 instance_count) override; void Draw(bool is_indexed, u32 instance_count) override;
void Clear() override; void Clear(u32 layer_count) override;
void DispatchCompute() override; void DispatchCompute() override;
void ResetCounter(VideoCore::QueryType type) override; void ResetCounter(VideoCore::QueryType type) override;
void Query(GPUVAddr gpu_addr, VideoCore::QueryType type, std::optional<u64> timestamp) override; void Query(GPUVAddr gpu_addr, VideoCore::QueryType type, std::optional<u64> timestamp) override;

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@ -213,7 +213,7 @@ void RasterizerVulkan::Draw(bool is_indexed, u32 instance_count) {
EndTransformFeedback(); EndTransformFeedback();
} }
void RasterizerVulkan::Clear() { void RasterizerVulkan::Clear(u32 layer_count) {
MICROPROFILE_SCOPE(Vulkan_Clearing); MICROPROFILE_SCOPE(Vulkan_Clearing);
if (!maxwell3d->ShouldExecute()) { if (!maxwell3d->ShouldExecute()) {
@ -256,7 +256,7 @@ void RasterizerVulkan::Clear() {
.rect = regs.clear_control.use_scissor ? GetScissorState(regs, 0, up_scale, down_shift) .rect = regs.clear_control.use_scissor ? GetScissorState(regs, 0, up_scale, down_shift)
: default_scissor, : default_scissor,
.baseArrayLayer = regs.clear_surface.layer, .baseArrayLayer = regs.clear_surface.layer,
.layerCount = 1, .layerCount = layer_count,
}; };
if (clear_rect.rect.extent.width == 0 || clear_rect.rect.extent.height == 0) { if (clear_rect.rect.extent.width == 0 || clear_rect.rect.extent.height == 0) {
return; return;

View file

@ -65,7 +65,7 @@ public:
~RasterizerVulkan() override; ~RasterizerVulkan() override;
void Draw(bool is_indexed, u32 instance_count) override; void Draw(bool is_indexed, u32 instance_count) override;
void Clear() override; void Clear(u32 layer_count) override;
void DispatchCompute() override; void DispatchCompute() override;
void ResetCounter(VideoCore::QueryType type) override; void ResetCounter(VideoCore::QueryType type) override;
void Query(GPUVAddr gpu_addr, VideoCore::QueryType type, std::optional<u64> timestamp) override; void Query(GPUVAddr gpu_addr, VideoCore::QueryType type, std::optional<u64> timestamp) override;