lvella/suyu
1
0
Fork 0
forked from suyu/suyu
Code Pull requests Activity

arm_dyncom_interpreter: Simplify assignment in SMLAW

Browse source 
Also a side-benefit of not having implementation-defined behavior.
This commit is contained in:
Lioncash 2015-07-16 22:08:07 -04:00
parent 078bf29d1d
commit 23dbbb786a
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
View file

@ -5695,7 +5695,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF);
const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16);
RD = (result & (0xFFFFFFFFFFFFFFFFLL >> 15)) >> 16;
RD = BITS(result, 16, 47);
if ((result >> 16) != (s32)RD)
cpu->Cpsr |= (1 << 27);