lvella/suyu
1
0
Fork 0
forked from suyu/suyu
Code Pull requests Activity

arm_dynarmic_64: Invalidate on all cores

Browse source
This commit is contained in:
merry 2022-03-27 15:37:19 +01:00
parent 3a9a0d9cb3
commit 1383441b15
1 changed files with 4 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/core/arm/dynarmic/arm_dynarmic_64.cpp
View file

@ -93,17 +93,19 @@ public:
static constexpr u64 ICACHE_LINE_SIZE = 64; static constexpr u64 ICACHE_LINE_SIZE = 64;
const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1); const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE); parent.system.InvalidateCpuInstructionCacheRange(cache_line_start, ICACHE_LINE_SIZE);
break; break;
} }
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU: case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
parent.ClearInstructionCache(); parent.system.InvalidateCpuInstructionCaches();
break; break;
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable: case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
default: default:
LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op); LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
break; break;
} }
parent.jit->HaltExecution();
} }
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override { void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {