forked from suyu/suyu
b1d5db1cf6
# Conflicts: # src/core/CMakeLists.txt # src/core/arm/dynarmic/arm_dynarmic.cpp # src/core/arm/dyncom/arm_dyncom.cpp # src/core/hle/kernel/process.cpp # src/core/hle/kernel/thread.cpp # src/core/hle/kernel/thread.h # src/core/hle/kernel/vm_manager.cpp # src/core/loader/3dsx.cpp # src/core/loader/elf.cpp # src/core/loader/ncch.cpp # src/core/memory.cpp # src/core/memory.h # src/core/memory_setup.h
171 lines
4.6 KiB
C++
171 lines
4.6 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include "common/common_types.h"
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#include "core/hle/kernel/vm_manager.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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#include "core/arm/skyeye_common/vfp/asm_vfp.h"
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/// Generic ARM11 CPU interface
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class ARM_Interface : NonCopyable {
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public:
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virtual ~ARM_Interface() {}
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struct ThreadContext {
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u64 cpu_registers[30];
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u64 lr;
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u64 sp;
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u64 pc;
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u64 cpsr;
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u128 fpu_registers[32];
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u64 fpscr;
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u64 fpexc;
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// TODO(bunnei): Fix once we have proper support for tpidrro_el0, etc. in the JIT
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VAddr tls_address;
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};
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/**
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* Runs the CPU for the given number of instructions
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* @param num_instructions Number of instructions to run
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*/
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void Run(int num_instructions) {
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ExecuteInstructions(num_instructions);
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this->num_instructions += num_instructions;
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}
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/// Step CPU by one instruction
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void Step() {
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Run(1);
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}
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virtual void MapBackingMemory(VAddr address, size_t size, u8* memory, Kernel::VMAPermission perms) {}
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/// Clear all instruction cache
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virtual void ClearInstructionCache() = 0;
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/// Notify CPU emulation that page tables have changed
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virtual void PageTableChanged() = 0;
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/**
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* Set the Program Counter to an address
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* @param addr Address to set PC to
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*/
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virtual void SetPC(u64 addr) = 0;
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/*
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* Get the current Program Counter
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* @return Returns current PC
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*/
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virtual u64 GetPC() const = 0;
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/**
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* Get an ARM register
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* @param index Register index
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* @return Returns the value in the register
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*/
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virtual u64 GetReg(int index) const = 0;
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/**
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* Set an ARM register
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* @param index Register index
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* @param value Value to set register to
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*/
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virtual void SetReg(int index, u64 value) = 0;
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virtual const u128& GetExtReg(int index) const = 0;
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virtual void SetExtReg(int index, u128& value) = 0;
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/**
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* Gets the value of a VFP register
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* @param index Register index (0-31)
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* @return Returns the value in the register
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*/
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virtual u32 GetVFPReg(int index) const = 0;
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/**
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* Sets a VFP register to the given value
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* @param index Register index (0-31)
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* @param value Value to set register to
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*/
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virtual void SetVFPReg(int index, u32 value) = 0;
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/**
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* Gets the current value within a given VFP system register
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* @param reg The VFP system register
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* @return The value within the VFP system register
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*/
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virtual u32 GetVFPSystemReg(VFPSystemRegister reg) const = 0;
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/**
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* Sets the VFP system register to the given value
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* @param reg The VFP system register
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* @param value Value to set the VFP system register to
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*/
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virtual void SetVFPSystemReg(VFPSystemRegister reg, u32 value) = 0;
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/**
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* Get the current CPSR register
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* @return Returns the value of the CPSR register
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*/
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virtual u32 GetCPSR() const = 0;
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/**
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* Set the current CPSR register
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* @param cpsr Value to set CPSR to
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*/
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virtual void SetCPSR(u32 cpsr) = 0;
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/**
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* Gets the value stored in a CP15 register.
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* @param reg The CP15 register to retrieve the value from.
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* @return the value stored in the given CP15 register.
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*/
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virtual u32 GetCP15Register(CP15Register reg) = 0;
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/**
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* Stores the given value into the indicated CP15 register.
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* @param reg The CP15 register to store the value into.
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* @param value The value to store into the CP15 register.
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*/
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virtual void SetCP15Register(CP15Register reg, u32 value) = 0;
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virtual VAddr GetTlsAddress() const = 0;
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virtual void SetTlsAddress(VAddr address) = 0;
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/**
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* Saves the current CPU context
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* @param ctx Thread context to save
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*/
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virtual void SaveContext(ThreadContext& ctx) = 0;
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/**
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* Loads a CPU context
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* @param ctx Thread context to load
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*/
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virtual void LoadContext(const ThreadContext& ctx) = 0;
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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virtual void PrepareReschedule() = 0;
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/// Getter for num_instructions
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u64 GetNumInstructions() const {
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return num_instructions;
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}
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protected:
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/**
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* Executes the given number of instructions
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* @param num_instructions Number of instructions to executes
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*/
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virtual void ExecuteInstructions(int num_instructions) = 0;
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private:
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u64 num_instructions = 0; ///< Number of instructions executed
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};
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