forked from suyu/suyu
shader: Refactor half floating instructions
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parent
f91859efd2
commit
e802512d8e
4 changed files with 84 additions and 58 deletions
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@ -78,6 +78,8 @@ add_library(shader_recompiler STATIC
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frontend/maxwell/translate/impl/floating_point_range_reduction.cpp
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frontend/maxwell/translate/impl/floating_point_set_predicate.cpp
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frontend/maxwell/translate/impl/half_floating_point_add.cpp
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frontend/maxwell/translate/impl/half_floating_point_helper.cpp
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frontend/maxwell/translate/impl/half_floating_point_helper.h
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frontend/maxwell/translate/impl/impl.cpp
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frontend/maxwell/translate/impl/impl.h
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frontend/maxwell/translate/impl/integer_add.cpp
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@ -2,66 +2,10 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/common_types.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_encoding.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_helper.h"
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namespace Shader::Maxwell {
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namespace {
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enum class Merge : u64 {
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H1_H0,
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F32,
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MRG_H0,
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MRG_H1,
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};
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enum class Swizzle : u64 {
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H1_H0,
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F32,
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H0_H0,
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H1_H1,
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};
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std::pair<IR::F16F32F64, IR::F16F32F64> Extract(IR::IREmitter& ir, IR::U32 value, Swizzle swizzle) {
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switch (swizzle) {
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case Swizzle::H1_H0: {
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const IR::Value vector{ir.UnpackFloat2x16(value)};
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return {IR::F16{ir.CompositeExtract(vector, 0)}, IR::F16{ir.CompositeExtract(vector, 1)}};
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}
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case Swizzle::H0_H0: {
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const IR::F16 scalar{ir.CompositeExtract(ir.UnpackFloat2x16(value), 0)};
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return {scalar, scalar};
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}
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case Swizzle::H1_H1: {
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const IR::F16 scalar{ir.CompositeExtract(ir.UnpackFloat2x16(value), 1)};
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return {scalar, scalar};
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}
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case Swizzle::F32: {
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const IR::F32 scalar{ir.BitCast<IR::F32>(value)};
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return {scalar, scalar};
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}
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}
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throw InvalidArgument("Invalid swizzle {}", swizzle);
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}
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IR::U32 MergeResult(IR::IREmitter& ir, IR::Reg dest, const IR::F16& lhs, const IR::F16& rhs,
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Merge merge) {
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switch (merge) {
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case Merge::H1_H0:
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return ir.PackFloat2x16(ir.CompositeConstruct(lhs, rhs));
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case Merge::F32:
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return ir.BitCast<IR::U32, IR::F32>(ir.FPConvert(32, lhs));
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case Merge::MRG_H0:
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case Merge::MRG_H1: {
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const IR::Value vector{ir.UnpackFloat2x16(ir.GetReg(dest))};
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const bool h0{merge == Merge::MRG_H0};
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const IR::F16& insert{h0 ? lhs : rhs};
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return ir.PackFloat2x16(ir.CompositeInsert(vector, insert, h0 ? 0 : 1));
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}
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}
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throw InvalidArgument("Invalid merge {}", merge);
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}
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void HADD2(TranslatorVisitor& v, u64 insn, Merge merge, bool ftz, bool sat, bool abs_a, bool neg_a,
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Swizzle swizzle_a, bool abs_b, bool neg_b, Swizzle swizzle_b, const IR::U32& src_b) {
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@ -122,7 +66,7 @@ void HADD2(TranslatorVisitor& v, u64 insn, bool sat, bool abs_b, bool neg_b, Swi
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HADD2(v, insn, hadd2.merge, hadd2.ftz != 0, sat, hadd2.abs_a != 0, hadd2.neg_a != 0,
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hadd2.swizzle_a, abs_b, neg_b, swizzle_b, src_b);
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}
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} // Anonymous namespace
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} // namespace
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void TranslatorVisitor::HADD2_reg(u64 insn) {
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union {
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@ -0,0 +1,49 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_helper.h"
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namespace Shader::Maxwell {
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std::pair<IR::F16F32F64, IR::F16F32F64> Extract(IR::IREmitter& ir, IR::U32 value, Swizzle swizzle) {
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switch (swizzle) {
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case Swizzle::H1_H0: {
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const IR::Value vector{ir.UnpackFloat2x16(value)};
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return {IR::F16{ir.CompositeExtract(vector, 0)}, IR::F16{ir.CompositeExtract(vector, 1)}};
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}
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case Swizzle::H0_H0: {
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const IR::F16 scalar{ir.CompositeExtract(ir.UnpackFloat2x16(value), 0)};
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return {scalar, scalar};
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}
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case Swizzle::H1_H1: {
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const IR::F16 scalar{ir.CompositeExtract(ir.UnpackFloat2x16(value), 1)};
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return {scalar, scalar};
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}
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case Swizzle::F32: {
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const IR::F32 scalar{ir.BitCast<IR::F32>(value)};
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return {scalar, scalar};
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}
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}
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throw InvalidArgument("Invalid swizzle {}", swizzle);
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}
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IR::U32 MergeResult(IR::IREmitter& ir, IR::Reg dest, const IR::F16& lhs, const IR::F16& rhs,
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Merge merge) {
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switch (merge) {
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case Merge::H1_H0:
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return ir.PackFloat2x16(ir.CompositeConstruct(lhs, rhs));
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case Merge::F32:
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return ir.BitCast<IR::U32, IR::F32>(ir.FPConvert(32, lhs));
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case Merge::MRG_H0:
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case Merge::MRG_H1: {
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const IR::Value vector{ir.UnpackFloat2x16(ir.GetReg(dest))};
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const bool h0{merge == Merge::MRG_H0};
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const IR::F16& insert{h0 ? lhs : rhs};
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return ir.PackFloat2x16(ir.CompositeInsert(vector, insert, h0 ? 0 : 1));
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}
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}
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throw InvalidArgument("Invalid merge {}", merge);
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}
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} // namespace Shader::Maxwell
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@ -0,0 +1,31 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/common_types.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_encoding.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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enum class Merge : u64 {
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H1_H0,
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F32,
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MRG_H0,
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MRG_H1,
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};
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enum class Swizzle : u64 {
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H1_H0,
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F32,
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H0_H0,
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H1_H1,
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};
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std::pair<IR::F16F32F64, IR::F16F32F64> Extract(IR::IREmitter& ir, IR::U32 value, Swizzle swizzle);
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IR::U32 MergeResult(IR::IREmitter& ir, IR::Reg dest, const IR::F16& lhs, const IR::F16& rhs,
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Merge merge);
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} // namespace Shader::Maxwell
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