forked from suyu/suyu
GPU: Do periodic VBlank updates using CoreTiming
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parent
e29dd76e12
commit
9e084826b8
3 changed files with 43 additions and 50 deletions
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@ -9,6 +9,7 @@
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#include "core/settings.h"
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#include "core/settings.h"
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#include "core/core.h"
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#include "core/core.h"
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#include "core/mem_map.h"
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#include "core/mem_map.h"
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#include "core/core_timing.h"
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#include "core/hle/hle.h"
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#include "core/hle/hle.h"
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#include "core/hle/service/gsp_gpu.h"
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#include "core/hle/service/gsp_gpu.h"
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@ -24,12 +25,17 @@ namespace GPU {
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Regs g_regs;
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Regs g_regs;
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bool g_skip_frame = false; ///< True if the current frame was skipped
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/// True if the current frame was skipped
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bool g_skip_frame = false;
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static u64 frame_ticks = 0; ///< 268MHz / gpu_refresh_rate frames per second
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/// 268MHz / gpu_refresh_rate frames per second
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static u64 last_update_tick = 0; ///< CPU ticl count from last GPU update
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static u64 frame_ticks;
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static u64 frame_count = 0; ///< Number of frames drawn
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/// Event id for CoreTiming
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static bool last_skip_frame = false; ///< True if the last frame was skipped
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static int vblank_event;
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/// Total number of frames drawn
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static u64 frame_count;
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/// True if the last frame was skipped
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static bool last_skip_frame = false;
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template <typename T>
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template <typename T>
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inline void Read(T &var, const u32 raw_addr) {
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inline void Read(T &var, const u32 raw_addr) {
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@ -192,21 +198,9 @@ template void Write<u16>(u32 addr, const u16 data);
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template void Write<u8>(u32 addr, const u8 data);
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template void Write<u8>(u32 addr, const u8 data);
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/// Update hardware
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/// Update hardware
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void Update() {
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static void VBlankCallback(u64 userdata, int cycles_late) {
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auto& framebuffer_top = g_regs.framebuffer_config[0];
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auto& framebuffer_top = g_regs.framebuffer_config[0];
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// Synchronize GPU on a thread reschedule: Because we cannot accurately predict a vertical
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// blank, we need to simulate it. Based on testing, it seems that retail applications work more
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// accurately when this is signalled between thread switches.
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u64 current_ticks = Core::g_app_core->GetTicks();
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if (HLE::g_reschedule) {
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// Synchronize frame...
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if ((current_ticks - last_update_tick) >= frame_ticks) {
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last_update_tick += frame_ticks;
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frame_count++;
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frame_count++;
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last_skip_frame = g_skip_frame;
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last_skip_frame = g_skip_frame;
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g_skip_frame = (frame_count & Settings::values.frame_skip) != 0;
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g_skip_frame = (frame_count & Settings::values.frame_skip) != 0;
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@ -234,8 +228,9 @@ void Update() {
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// until we can emulate DSP interrupts, this is probably the only reasonable place to do
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// until we can emulate DSP interrupts, this is probably the only reasonable place to do
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// this. Certain games expect this to be periodically signaled.
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// this. Certain games expect this to be periodically signaled.
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DSP_DSP::SignalInterrupt();
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DSP_DSP::SignalInterrupt();
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}
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}
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// Reschedule recurrent event
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CoreTiming::ScheduleEvent(frame_ticks - cycles_late, vblank_event);
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}
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}
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/// Initialize hardware
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/// Initialize hardware
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@ -269,10 +264,12 @@ void Init() {
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framebuffer_sub.active_fb = 0;
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framebuffer_sub.active_fb = 0;
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frame_ticks = 268123480 / Settings::values.gpu_refresh_rate;
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frame_ticks = 268123480 / Settings::values.gpu_refresh_rate;
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last_update_tick = Core::g_app_core->GetTicks();
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last_skip_frame = false;
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last_skip_frame = false;
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g_skip_frame = false;
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g_skip_frame = false;
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vblank_event = CoreTiming::RegisterEvent("GPU::VBlankCallback", VBlankCallback);
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CoreTiming::ScheduleEvent(frame_ticks, vblank_event);
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LOG_DEBUG(HW_GPU, "initialized OK");
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LOG_DEBUG(HW_GPU, "initialized OK");
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}
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}
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@ -252,9 +252,6 @@ void Read(T &var, const u32 addr);
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template <typename T>
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template <typename T>
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void Write(u32 addr, const T data);
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void Write(u32 addr, const T data);
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/// Update hardware
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void Update();
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/// Initialize hardware
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/// Initialize hardware
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void Init();
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void Init();
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@ -75,7 +75,6 @@ template void Write<u8>(u32 addr, const u8 data);
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/// Update hardware
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/// Update hardware
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void Update() {
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void Update() {
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GPU::Update();
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}
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}
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/// Initialize hardware
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/// Initialize hardware
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